ADIS16COM1SLASHPCBZ datasheet(10/37 Pages) AD

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ADIS16000/ADIS16229

Preliminary Technical Data

Rev. PrA | Page 10 of 37

ADIS16000 BASIC OPERATION

Once it has appropriate power on the VDD pin, the ADIS16000

will automatically begin a self-initialization process. Once this

process is complete, the SPI interface activates and provides

access to its register structure. The SPI interface supports

connectivity with most embedded processor platforms, using

the connection diagram in Figure 10. The factory default

configuration for DO1 provides a busy indicator signal that

indicates when to avoid SPI communication requests.

Figure 10. Electrical Hook-Up Diagram

Table 7. Generic Master Processor Pin Names and Functions

Pin Name

Function

Slave select

SCLK

Serial clock

MOSI

Master output, slave input

MISO

Master input, slave output

IRQ1, IRQ2

Interrupt request inputs (optional)

The ADIS16000 SPI interface supports full duplex serial

communication (simultaneous transmit and receive) and uses

the bit sequence shown in Figure 14. Table 8 provides a list of

the most common settings that require attention to initialize

a processor serial port for the ADIS16000 SPI interface.

Table 8. Generic Master Processor SPI Settings

Processor Setting

Description

Master

The ADIS16000 operates as a slave.

SCLK Rate ≤ 2.5 MHz

Bit rate setting.

SPI Mode 3

Clock polarity/phase

(CPOL = 1, CPHA = 1).

MSB First

Bit sequence.

16-Bit

Shift register/data length.

Table 9 and Table 10 provide lists of user registers with their

lower byte addresses. Each register consists of two bytes that

each has its own unique 7-bit address. Figure 11 relates the bits

of each register to their upper and lower addresses.

UPPER BYTE

LOWER BYTE

Figure 11. Generic Register Bit Definitions

SPI WRITE COMMANDS

User control registers govern many internal operations. The

DIN bit sequence in Figure 14 provides the ability to write to

these registers, one byte at a time. Some configuration changes

and functions require only one write cycle. For example, set

PAGE_ID[7:0] = 1 (DIN = 0x8001) to select Page 1 of the

Figure 12. SPI Sequence for Selecting Page 1 for Access (DIN = 0x8001)

SPI READ COMMANDS

A single register read requires two 16-bit SPI cycles that also

use the bit assignments that are shown in Figure 14. The first

sequence sets R/W = 0 and communicates the target address

(Bits[A6:A0]). Bits[D7:D0] are don’t care bits for a read DIN

sequence. DOUT clocks out the requested register contents

during the second sequence. The second sequence can also use

DIN to set up the next read. Figure 13 provides a signal diagram

for all four SPI signals while reading the PROD_ID. In this

diagram, DIN = 0x1600 and DOUT reflects the decimal

equivalent of 16,000.

Figure 13. Example SPI Read, PROD_ID (Page 0), Second Sequence

R/W

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

DB10

DB11

DB12

DB13

DB14

DB15

NOTES

1. DOUT BITS ARE BASED ON THE PREVIOUS 16-BIT SEQUENCE (R/W = 0).

SCLK

DIN

DOUT

DB13

DB14

DB15

Figure 14. Example SPI Read Sequence

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