ADIS16COM1SLASHPCBZ datasheet(14/37 Pages) AD

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ADIS16000/ADIS16229

Preliminary Technical Data

Rev. PrA | Page 14 of 37

Table 15. RSSI_G

Page 0, Low Byte Address = 0x0A, Read Only

Bits

Description (Default = 0x)

[15:0]

Received signal strength

Twos complement format, 1 LSB = 1dBm

0x0000 = 0dBm

0xFFA2 = -94dBm

Table 16. RSSI_S

Page 1-6, Low Byte Address = 0x5A, Read Only

Bits

Description (Default = 0x1100)

[15:0]

Received signal strength

Twos complement format, 1 LSB = 1dBm

0x0000 = 0dBm

0xFFA2 = -94dBm

Transmission Power Control

Both ADIS16000 and ADIS16229 units provide controls for

transmission power in a registers called, TX_PWR_CTRL_G (see

Table 17) and TX_PWR_CTRL_S. The registers provide users

with the ability to optimize the transmission power for battery

optimization and to manage interference influence on other

networks. Note that compliance with FCC Part 15.249 involves

limiting the transmission power to -1dBm.

Table 17. TX_PWR_CTRL_G

Page 0, Low Byte Address = 0x08, Read/Write

Bits

Description (Default = 0x)

[15:5]

Not used (do not care)

[40]

Transmission power, offset binary format

1LSB = 1.6dBm (25.5/15)

0 = -15.5dBm (minimum)

F = +10dBm (maximum)

Table 18. TX_PWR_CTRL_S

Page 1-6, Low Byte Address = 0x58, Read/Write

Bits

Description (Default = 0x)

[15:5]

Not used (do not care)

[40]

Transmission power, offset binary format

1LSB = 1.6dBm (25.5/15)

0 = -15.5dBm (minimum)

F = +10dBm (maximum)

Wireless Configuration

The RF_MODE (see Table 19) register provides a number of

important wireless configuration parameters. Note that when the

transmission power exceeds -1dBm, FCC Part 15.247 requires the

use of “frequency-hopping.”

Table 19. RF_MODE

Page 0, Low Byte Address = 0x58, Read/Write

Bits

Description (Default = 0x)

[15:9]

Not used (do not care)

[8]

Complete register dump during update cycle

(0 = enable, 1 = disable)

[7]

Periodic wake-up/beacon synchronization

(0 = disable, 1 = enable)

[6]

Frequency hoping

(0 = disable, 1 = enable)

[5]

Complete synchronization after missing 2 beacons

(0 = disable, 1 = enable)

[4:2]

Not used (do not care)

[1]

Update gateway on Alarm only

(0 = disable, 1 = enable)

[0]

Update gateway on beacon synchronization

(0 = disable, 1 = enable)

The UPDAT_INT (See Table 20) and INT_SCL (See Table 21)

registers establish the time between wake-up events, where the

remote ADIS16229 captures data, analyzes it and communicates

the information.

Table 20. UPDAT_INT

Page 1-6, Low Byte Address = 0x5E, Read/Write

Bits

Description (Default = 0x)

[15:0]

Offset binary number, scale factor set by INT_SCL

Table 21. INT_SCL

Page 1-6, Low Byte Address = 0x60, Read/Write

Bits

Description (Default = 0x)

[15:2]

Not used (do not care)

[1:0]

Scale factor

00 = 30.52μsec/LSB, maximum = 2 seconds

01 = 0.488msc/LSB, maximum = 31.98 seconds

10 = 1/128 sec/LSB, maximum = 512 seconds

11 = 1 sec/LSB, maximum = 18.2 hours

The beacon synchronization function uses periodic monitoring

for drift in sensor node clocks and limits their sleep time to 30

minutes (or less) in order to maintain consistent

synchronization. The BEACON_SETUP (See Table 22) register

provides a user control for this function. When operating in

real-time mode (REC_CTRL1 register, See Table 27) this mode

is not necessary and automatically turns off.

Table 22. BEACON_SETUP

Page 0, Low Byte Address = 0x10, Read/Write

Bits

Description (Default = 0x)

[15:1]

Not used

1 = Beacon synchronization enable

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