ADP7182ACPZ-R7 datasheet(20/28 Pages) ANACHIP

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ADP7182

Data Sheet

Rev. A | Page 20 of 28

THEORY OF OPERATION

The ADP7182 is a low quiescent current, LDO linear regulator

that operates from −2.7 V to −28 V and can provide up to −200 mA

of output current. Drawing a low −650 µA of quiescent current

(typical) at full load makes the ADP7182 ideal for battery-powered

portable equipment. Maximum shutdown current consumption

is −8 µA at room temperature.

Optimized for use with small 2.2 µF ceramic capacitors, the

ADP7182 provides excellent transient performance.

VOUT

GND

VIN

REFERENCE

SHUTDOWN

SHORT

CIRCUIT

THERMAL

PROTECT

VREG

Figure 75. Fixed Output Voltage Internal Block Diagram

VOUT

ADJ

GND

VIN

–1.22V

REFERENCE

SHUTDOWN

SHORT

CIRCUIT

THERMAL

PROTECT

VREG

Figure 76. Adjustable Output Voltage Internal Block Diagram

Internally, the ADP7182 consists of a reference, an error amplifier,

a feedback voltage divider, and an NMOS pass transistor.

Output current is delivered via the NMOS pass transistor,

which is controlled by the error amplifier. The error amplifier

compares the reference voltage with the feedback voltage from

the output and amplifies the difference. If the feedback voltage is

more positive than the reference voltage, the gate of the NMOS

transistor is pulled toward GND, allowing more current to pass

and increasing the output voltage. If the feedback voltage is more

negative than the reference voltage, the gate of the NMOS

transistor is pulled toward −VIN, allowing less current to pass

and decreasing the output voltage.

The ESD protection devices are shown in the block diagram as

Zener diodes (see Figure 75 and Figure 76).

ENABLE PIN OPERATION

The ADP7182 uses the EN pin to enable and disable the VOUT

pin under normal operating conditions. When EN is at ±2 V with

respect to GND, VOUT turns on, and when EN is at 0 V, VOUT

turns off. For automatic startup, EN can be connected to VIN.

ADJUSTABLE MODE OPERATION

The ADP7182 is available in a fixed output voltage and an

adjustable mode version with an output voltage that can be set

to between −1.22 V and −27 V by an external voltage divider. The

output voltage can be set according to

−VOUT = −1.22 V (1 + RFB1/RFB2)

RFB2 must be less than 120 kΩ to minimize the output voltage errors

due to the leakage current of the ADJ pin. The error voltage

caused by the ADJ pin leakage current is the parallel combination

of RFB1 and RFB2 times the ADJ pin leakage current.

For example, when RFB1 = RFB2 = 120 kΩ, the output voltage is

−2.44 V and the error due to the typical ADJ pin leakage current

(10 nA) is 60 kΩ times 10 nA, or 6 mV. This example results in

an output voltage error of 0.245%.

The addition of a small capacitor (~100 pF) in parallel with

RFB1 can improve the stability of the ADP7182. Larger values of

capacitance also reduce the noise and improve PSRR (see the

Noise Reduction of the Adjustable ADP7182 section).

RFB2

120kΩ

RFB1

120kΩ

GND

ADJ

VIN

VOUT

ADP7182

–2V

OFF

VIN = –3V

VOUT = –2.44V

COUT

2.2µF

CIN

2.2µF

Figure 77. Setting Adjustable Output Voltage

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