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ADP7182ACPZ-R7 数据表(PDF) 22 Page - Anachip Corp

部件名 ADP7182ACPZ-R7
功能描述  ??8 V, ??00 mA, Low Noise, Linear Regulator
PDF  28 Pages
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制造商  ANACHIP [Anachip Corp]
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标志 ANACHIP - Anachip Corp

ADP7182ACPZ-R7 数据表(HTML) 22 Page - Anachip Corp

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ADP7182
Data Sheet
Rev. A | Page 22 of 28
ENABLE PIN OPERATION
The ADP7182 provides a dual polarity enable pin (EN) that turns
on the LDO when |VEN| ≥ 2 V. The enable voltage can be positive or
negative with respect to ground.
0
–2.0
–1.5
–1.0
–0.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
ENABLE VOLTAGE (V)
VOUT WITH RISING VEN
VOUT WITH FALLING VEN
Figure 80. Typical EN Pin Operation
Figure 80 shows the typical hysteresis of the EN pin. This prevents
on/off oscillations that can occur due to noise on the EN pin as
it passes through the threshold points.
Figure 81 shows typical EN thresholds when the input voltage
varies from −2.7 V to −28 V.
1.0
–2.0
–1.5
–1.0
–0.5
0
0.5
–30
–26
–22
–18
–14
–10
–6
–2
INPUT VOLTAGE (V)
ENABLE+
DISABLE+
ENABLE–
DISABLE–
Figure 81. Typical EN Pin Thresholds vs. Input Voltage
Figure 82 and Figure 83 show the start-up behavior for a −5 V
output with positive and negative going enable signals.
CH1 500mV BW
CH2 500mV BW
M40µs
A CH1
590mV
T 10.20%
1
2
T
EN
VOUT
Figure 82. Typical Start-Up Behavior, Positive Going Enable
CH1 500mV BW
CH2 500mV BW
M40µs A CH1
–580mV
T 10.20%
1
2
T
EN
VOUT
Figure 83. Typical Start-Up Behavior, Negative Going Enable
SOFT START
The ADP7182 uses an internal soft start to limit the inrush current
when the output is enabled. The start-up time for the −5 V option
is approximately 450 µs from the time the EN active threshold is
crossed to when the output reaches 90% of its final value. As shown
in Figure 84, the start-up time is dependent on the output voltage
setting.
2
–6
–5
–4
–3
–2
–1
0
1
0
1000
900
800
700
600
500
400
300
200
100
TIME (µs)
VEN
VOUT = –1.22V
VOUT = –3V
VOUT = –5V
Figure 84. Typical Start-Up Behavior, Different Output Voltages



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