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INTEDG 数据表(PDF) 378 Page - Microchip Technology |
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INTEDG 数据表(HTML) 378 Page - Microchip Technology |
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378 / 478 page  PIC16(L)F1946/47 DS41414D-page 378 2010-2012 Microchip Technology Inc. TABLE 29-3: PIC16(L)F1946/47 ENHANCED INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 14-Bit Opcode Status Affected Notes MSb LSb CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine 2 2 2 2 2 2 2 2 11 00 10 00 10 00 11 00 001k 0000 0kkk 0000 1kkk 0000 0100 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 INHERENT OPERATIONS CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Clear Watchdog Timer No Operation Load OPTION_REG register with W Software device Reset Go into Standby mode Load TRIS register with W 1 1 1 1 1 1 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0110 0000 0110 0000 0110 0110 0100 0000 0010 0001 0011 0fff TO, PD TO, PD C-COMPILER OPTIMIZED ADDFSR MOVIW MOVWI n, k n mm k[n] n mm k[n] Add Literal k to FSRn Move Indirect FSRn to W with pre/post inc/dec modifier, mm Move INDFn to W, Indexed Indirect. Move W to Indirect FSRn with pre/post inc/dec modifier, mm Move W to INDFn, Indexed Indirect. 1 1 1 1 1 11 00 11 00 11 0001 0000 1111 0000 1111 0nkk 0001 0nkk 0001 1nkk kkkk 0nmm kkkk 1nmm kkkk Z Z 2, 3 2 2, 3 2 Note 1:If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 3: See Table in the MOVIW and MOVWI instruction descriptions. |
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