INTEDG datasheet(116/478 Pages) MICROCHIP

116 / 478 page

PIC16(L)F1946/47

DS41414D-page 116

 2010-2012 Microchip Technology Inc.

11.3.2

ERASING FLASH PROGRAM

MEMORY

While executing code, program memory can only be

erased by rows. To erase a row:

Load the EEADRH:EEADRL register pair with

the address of new row to be erased.

Clear the CFGS bit of the EECON1 register.

Set the EEPGD, FREE, and WREN bits of the

EECON1 register.

Write 55h, then AAh, to EECON2 (Flash

programming unlock sequence).

Set control bit WR of the EECON1 register to

begin the erase operation.

Poll the FREE bit in the EECON1 register to

determine when the row erase has completed.

See Example 11-4.

After the “BSF EECON1,WR” instruction, the processor

requires two cycles to set up the erase operation. The

user must place two NOP instructions after the WR bit is

set. The processor will halt internal operations for the

typical 2 ms erase time. This is not Sleep mode as the

clocks and peripherals will continue to run. After the

erase cycle, the processor will resume operation with

the third instruction after the EECON1 write instruction.

11.3.3

WRITING TO FLASH PROGRAM

MEMORY

Program memory is programmed using the following

steps:

Load the starting address of the word(s) to be

programmed.

Load the write latches with data.

Initiate a programming operation.

Repeat steps 1 through 3 until all data is written.

Before writing to program memory, the word(s) to be

written must be erased or previously unwritten. Pro-

gram memory can only be erased one row at a time. No

automatic erase occurs upon the initiation of the write.

Program memory can be written one or more words at

a time. The maximum number of words written at one

time is equal to the number of write latches. See

Figure 11-2 (block writes to program memory with 16

write latches) for more details. The write latches are

aligned to the address boundary defined by EEADRL

as shown in Table 11-1. Write operations do not cross

these boundaries. At the completion of a program

memory write operation, the write latches are reset to

contain 0x3FFF.

The following steps should be completed to load the

write latches and program a block of program memory.

These steps are divided into two parts. First, all write

latches are loaded with data except for the last program

memory location. Then, the last write latch is loaded

and the programming sequence is initiated. A special

unlock sequence is required to load a write latch with

data or initiate a Flash programming operation. This

unlock sequence should not be interrupted.

Set the EEPGD and WREN bits of the EECON1

Clear the CFGS bit of the EECON1 register.

Set the LWLO bit of the EECON1 register. When

the LWLO bit of the EECON1 register is ‘1’, the

write sequence will only load the write latches

and will not initiate the write to Flash program

memory.

Load the EEADRH:EEADRL register pair with

the address of the location to be written.

Load the EEDATH:EEDATL register pair with

the program memory data to be written.

Write 55h, then AAh, to EECON2, then set the

WR bit of the EECON1 register (Flash

programming unlock sequence). The write latch

is now loaded.

Increment the EEADRH:EEADRL register pair

to point to the next location.

Repeat steps 5 through 7 until all but the last

write latch has been loaded.

Clear the LWLO bit of the EECON1 register.

When the LWLO bit of the EECON1 register is

‘0’, the write sequence will initiate the write to

Flash program memory.

10. Load the EEDATH:EEDATL register pair with

the program memory data to be written.

11. Write 55h, then AAh, to EECON2, then set the

WR bit of the EECON1 register (Flash

programming unlock sequence). The entire

latch block is now written to Flash program

memory.

It is not necessary to load the entire write latch block

with user program data. However, the entire write latch

block will be written to program memory.

An example of the complete write sequence for eight

words is shown in Example 11-5. The initial address is

loaded into the EEADRH:EEADRL register pair; the

eight words of data are loaded using indirect

addressing.

Note:

The

code

sequence

provided

Example 11-5 must be repeated multiple

times to fully program an erased program

memory row.

INTEDG 数据表(PDF) 116 Page - Microchip Technology

INTEDG 数据表(HTML) 116 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载