INTEDG datasheet(148/478 Pages) MICROCHIP

148 / 478 page

PIC16(L)F1946/47

DS41414D-page 148

 2010-2012 Microchip Technology Inc.

12.15 PORTG Registers

PORTG is an 8-bit wide, bidirectional port. The

corresponding data direction register is TRISG

(Register 12-25). Setting a TRISG bit (= 1) will make the

corresponding PORTG pin an input (i.e., put the

corresponding output driver in a High-Impedance mode).

Clearing a TRISG bit (= 0) will make the corresponding

PORTG pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

The exception is RG5, which is input only and its TRIS

bit will always read as ‘1’. Example 12-1 shows how to

initialize an I/O port.

Reading the PORTG register (Register 12-24) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written

to the PORT data latch (LATG). RG5 reads ‘0’ when

MCLRE = 1.

The TRISG register (Register 12-25) controls the

PORTG pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits

in the TRISG register are maintained set when using

them as analog inputs. I/O pins configured as analog

inputs always read ‘0’.

12.15.1

ANSELG REGISTER

The ANSELG register (Register 12-27) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELG bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

The state of the ANSELG bits has no effect on digital

output functions. A pin with TRIS clear and ANSEL set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affected port.

12.15.2

PORTG FUNCTIONS AND OUTPUT

PRIORITIES

Each PORTG pin is multiplexed with other functions. The

pins, their combined functions and their output priorities

are shown in Table 12-16.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the highest priority.

Analog input and some digital input functions are not

included in the list below. These input functions can

remain active when the pin is configured as an output.

Certain digital input functions override other port

functions and are included in the priority list.

Note:

The ANSELG register must be initialized

to configure an analog channel as a digital

input. Pins configured as analog inputs

will read ‘0’.

TABLE 12-16: PORTG OUTPUT PRIORITY

Pin Name

Function Priority(1)

RG0

CCP3 (CCP)

P3A (CCP)

SEG42 (LCD)

RG0

RG1

TX2 (EUSART)

CK2 (EUSART)

C3OUT (Comparator)

SEG43 (LCD)

RG1

RG2

DT2

SEG44 (LCD)

RG2

RG3

CCP4 (CCP)

P3D (CCP)

SEG45 (LCD)

RG3

RG4

CCP5 (CCP)

P1D (CCP)

SEG26 (LCD)

RG4

RG5

Input-only pin

Note 1:

Priority listed from highest to lowest.

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