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INTEDG 数据表(PDF) 144 Page - Microchip Technology |
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INTEDG 数据表(HTML) 144 Page - Microchip Technology |
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144 / 478 page  PIC16(L)F1946/47 DS41414D-page 144 2010-2012 Microchip Technology Inc. TABLE 12-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE REGISTER 12-18: LATE: PORTE DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 LATE<7:0> : PORTE Output Latch Value bits(1) Note 1: Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is return of actual I/O pin values. REGISTER 12-19: ANSELE: PORTE ANALOG SELECT REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — — — ANSE2 ANSE1 ANSE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ANSE<7:0> : Analog Select between Analog or Digital Function on Pins RE<7:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page APFCON P3CSEL P3BSEL P2DSEL P2CSEL P2BSEL CCP2SEL P1CSEL P1BSEL 129 ANSELE — — — — — ANSE2 ANSE1 ANSE0 144 CCPxCON PxM<1:0>(1) DCxB<1:0> CCPxM<3:0> 238 LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 144 LCDCON LCDEN SLPEN WERR — CS<1:0> LMUX<1:0> 337 LCDREF LCDIRE LCDIRS LCDIRI — VLCD3PE VLCD2PE VLCD1PE — 339 LCDSE2 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 341 PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 143 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 143 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE. Note 1: Applies to ECCP modules only. |
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