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LCMXO2-256ZE-1SG32C 数据表(PDF) 59 Page - Lattice Semiconductor |
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LCMXO2-256ZE-1SG32C 数据表(HTML) 59 Page - Lattice Semiconductor |
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59 / 106 page  3-20 DC and Switching Characteristics MachXO2 Family Data Sheet Generic DDR4 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Aligned 9 tDVA Input Data Valid After ECLK MachXO2-640U, MachXO2-1200/U and larger devices, bottom side only — 0.290 — 0.320 — 0.345 UI tDVE Input Data Hold After ECLK 0.739 — 0.699 — 0.703 — UI fDATA DDRX4 Serial Input Data Speed — 756 — 630 — 524 Mbps fDDRX4 DDRX4 ECLK Frequency — 378 — 315 — 262 MHz fSCLK SCLK Frequency — 95 — 79 — 66 MHz Generic DDR4 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Centered 9 tSU Input Data Setup Before ECLK MachXO2-640U, MachXO2-1200/U and larger devices, bottom side only 0.233 — 0.219 — 0.198 — ns tHO Input Data Hold After ECLK 0.287 — 0.287 — 0.344 — ns fDATA DDRX4 Serial Input Data Speed — 756 — 630 — 524 Mbps fDDRX4 DDRX4 ECLK Frequency — 378 — 315 — 262 MHz fSCLK SCLK Frequency — 95 — 79 — 66 MHz 7:1 LVDS Inputs (GDDR71_RX.ECLK.7:1) 9 tDVA Input Data Valid After ECLK MachXO2-640U, MachXO2-1200/U and larger devices, bottom side only — 0.290 — 0.320 — 0.345 UI tDVE Input Data Hold After ECLK 0.739 — 0.699 — 0.703 — UI fDATA DDR71 Serial Input Data Speed — 756 — 630 — 524 Mbps fDDR71 DDR71 ECLK Frequency — 378 — 315 — 262 MHz fCLKIN 7:1 Input Clock Frequency (SCLK) (minimum limited by PLL) — 108 — 90 — 75 MHz Generic DDR Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Aligned 9 tDIA Output Data Invalid After CLK Output All MachXO2 devices, all sides — 0.520 — 0.550 — 0.580 ns tDIB Output Data Invalid Before CLK Output — 0.520 — 0.550 — 0.580 ns fDATA DDRX1 Output Data Speed — 300 — 250 — 208 Mbps fDDRX1 DDRX1 SCLK frequency — 150 — 125 — 104 MHz Generic DDR Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Centered 9 tDVB Output Data Valid Before CLK Output All MachXO2 devices, all sides 1.210 — 1.510 — 1.870 — ns tDVA Output Data Valid After CLK Output 1.210 — 1.510 — 1.870 — ns fDATA DDRX1 Output Data Speed — 300 — 250 — 208 Mbps fDDRX1 DDRX1 SCLK Frequency (minimum limited by PLL) — 150 — 125 — 104 MHz Generic DDRX2 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Aligned 9 tDIA Output Data Invalid After CLK Output MachXO2-640U, MachXO2-1200/U and larger devices, top side only — 0.200 — 0.215 — 0.230 ns tDIB Output Data Invalid Before CLK Output — 0.200 — 0.215 — 0.230 ns fDATA DDRX2 Serial Output Data Speed — 664 — 554 — 462 Mbps fDDRX2 DDRX2 ECLK frequency — 332 — 277 — 231 MHz fSCLK SCLK Frequency — 166 — 139 — 116 MHz Parameter Description Device -6 -5 -4 Units Min. Max. Min. Max. Min. Max. |
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