LCMXO2-256ZE-1SG32C datasheet(32/106 Pages) LATTICE

32 / 106 page

2-28

Architecture

MachXO2 Family Data Sheet

Figure 2-20. Embedded Function Block Interface

Hardened I

2C IP Core

Every MachXO2 device contains two I

2C IP cores. These are the primary and secondary I2C IP cores. Either of the

two cores can be configured either as an I

2C master or as an I2C slave. The only difference between the two IP

cores is that the primary core has pre-assigned I/O pins whereas users can assign I/O pins for the secondary core.

When the IP core is configured as a master it will be able to control other devices on the I

2C bus through the inter-

face. When the core is configured as the slave, the device will be able to provide I/O expansion to an I

2C Master.

The I

2C cores support the following functionality:

• Master and Slave operation

• 7-bit and 10-bit addressing

• Multi-master arbitration support

• Clock stretching

• Up to 400 KHz data transfer speed

• General call support

• Interface to custom logic through 8-bit WISHBONE interface

Embedded Function Block (EFB)

Core

Logic/

Routing

EFB

WISHBONE

Interface

I2C (Primary)

I2C (Secondary)

SPI

Timer/Counter

PLL0

PLL1

Configuration

Logic

UFM

I/Os for I2C

(Primary)

I/Os for SPI

I/Os for I2C

(Secondary)

Indicates connection

through core logic/routing.

Power

Control

LCMXO2-256ZE-1SG32C 数据表(PDF) 32 Page - Lattice Semiconductor

LCMXO2-256ZE-1SG32C 数据表(HTML) 32 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载