LCMXO2-256ZE-1SG32C datasheet(21/106 Pages) LATTICE

21 / 106 page

2-17

Architecture

MachXO2 Family Data Sheet

In DDR generic mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling

edge the registered D1 input is registered into the register Q1. A multiplexer running off the same clock is used to

switch the mux between the outputs of registers Q0 and Q1 that will then feed the output.

Figure 2-14 shows the output register block on the left, top and bottom edges.

Figure 2-14. MachXO2 Output Register Block Diagram (PIO on the Left, Top and Bottom Edges)

Right Edge

The output register block on the right edge is a superset of the output register on left, top and bottom edges of the

device. In addition to supporting SDR and Generic DDR modes, the output register blocks for PIOs on the right

edge include additional logic to support DDR-memory interfaces. Operation of this block is similar to that of the out-

put register block on other edges.

In DDR memory mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling

edge the registered D1 input is registered into the register Q1. A multiplexer running off the DQSW90 signal is used

to switch the mux between the outputs of registers Q0 and Q1 that will then feed the output.

Figure 2-15 shows the output register block on the right edge.

Output path

D/L Q

Tri-state path

D/L Q

SCLK

LCMXO2-256ZE-1SG32C 数据表(PDF) 21 Page - Lattice Semiconductor