AD6650SLASHPCB datasheet(35/44 Pages) AD

35 / 44 page

AD6650

Rev. A | Page 35 of 44

Reg.

(Hex)

Mnemonic

Bit

Width

Description

Additional Information

AGC Control 1

VGA gain (dB) = (0.094) × VGA gain word.

Code

Gain (dB)

0 dB

0.094 dB

0.188 dB

382

35.9 dB

8 to 0: VGA Gain

This drives the VGA directly when force VGA

gain = 1.

383

36.002 dB

AGC Control 2

AGC hysteresis and requested level.

Code

Hysteresis (dB)

15 to 8: Hysteresis

Upper hysteresis threshold = requested level

+ hysteresis.

±.094 dB

±.188 dB

Lower hysteresis threshold = requested level

− hysteresis.

254

±23.876 dB

The gain word does not change if the peak

measurement falls between the upper and

lower hysteresis threshold.

255

±23.97 dB

Code

Requested

Level (dBm)

7 to 0: Requested Level

+4 dBm

+3.906 dBm

+3.812 dBm

254

−19.8 dBm

The requested level for the slow loop. The

full-scale input into the AD6650 is

2 V p-p = 4 dBm.

255

−19.97 dBm

AGC Control 3

Loop gain = (mantissa/256) × ½exponent.

Code

Loop Gain Exp

10 to 8: Loop Gain

Exponent

Loop gain exponent (slow loop).

7 to 6: Reserved

Reserved.

N/A

Code

Mantissa

5 to 0: Loop Gain

Mantissa

Loop gain mantissa (slow loop).

AD6650/PCB 数据表(PDF) 35 Page - Analog Devices

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AD6650/PCB 数据表(PDF) 35 Page - Analog Devices

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