AD6650SLASHPCB datasheet(36/44 Pages) AD

36 / 44 page

AD6650

Rev. A | Page 36 of 44

Reg.

(Hex)

Mnemonic

Bit

Width

Description

Additional Information

AGC Control 4

Fast attack and fast decay loop parameters.

Code

Step size (dB)

12 to 10: FD_Step

Fast decay step size.

0 dB

0.094 dB

0.188 dB

0.564 dB

0.658 dB

Code

Threshold

9 to 8: FA_Thresh

−6.02 dBFS

−3.1 dBFS

−0.915 dBFS

Fast attack threshold measured at the

antialiasing filters.

0 dBFS

Code

Count

7 to 4: FA_Count

Fast attack count. The fast attack loop steps

the gain down by FA_Step for FA_Count

number of clock cycles.

Code

Step size (dB)

3 to 0: FA_Step

Fast attack step size.

0 dB

0.094 dB

0.188 dB

1.316 dB

1.41 dB

AGC Control 5

Slow loop peak detector period.

Code

Samples (fS

clock cycles)

254

15 to 8: SPB Peak

Detector Period

Signal plus blocker peak detector period for

the slow loop; fS = 26 MHz; fSYM =270.833 kHz;

SPB peak period = ¼ × (fSAMP/fSYM).

255

7 to 0: Reserved

Reserved.

Must be written 8’b00000000

Reserved

Reserved.

Must be written 7’b0000000

AGC Control 7

Code

Threshold

8 to 0: FD SPB Threshold

Fast decay signal plus blocker threshold.

0 dBFS

−0.094 dBFS

−0.188 dBFS

510

−47.94 dBFS

511

−48.034 dBFS

AD6650/PCB 数据表(PDF) 36 Page - Analog Devices

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AD6650/PCB 数据表(PDF) 36 Page - Analog Devices

AD6650/PCB 数据表(HTML) 36 Page - Analog Devices

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