AD6650SLASHPCB datasheet(23/44 Pages) AD

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AD6650

Rev. A | Page 23 of 44

AD6650

VLDO

867Ω

1.0µF

3900pF

56000pF

200Ω

Figure 28. Loop Filter Circuit

R-DIVIDER

N-DIVIDER

R-DIVIDER

DOWN

CHARGE

PUMP

CPGND

N-DIVIDER

CP OUTPUT

CLR2

ADP2

ADP1

CLR1

Figure 29. PFD Simplified Schematic and Timing (Locked)

LDO

The AD6650 includes an on-chip 2.6 V low dropout (LDO)

voltage regulator that supplies the VCO and other sections of

the PLL. A 0.22 μF bypass capacitor is required on the VLDO

output to ensure stability. This LDO employs the same technology

used in the anyCAP® line of regulators from Analog Devices, Inc.,

making it insensitive to the type of capacitor used. Driving an

external load from the VLDO output is not supported.

AGC LOOP/RELINEARIZATION

The AGC consists of three gain control loops: a slow loop, a fast

attack (FA) loop, and a fast decay (FD) loop.

ADC

AGC

STATE

MACHINE

UPPER

THRESHOLD

FAST LOOP DETECTORS

SLOW LOOP, SIGNAL LEVEL

SIGNAL PLUS BLOCKER LEVEL

ADC

Figure 30. AGC Loop Block Diagram

Slow Loop

The slow loop is the main loop and is associated with a loop

gain parameter. This parameter controls the rate of change of

the gain and should always be less than 1. To determine the

loop gain, Equation 19 should be used.

Exponent

Mantissa

AGCLoopGai

−

⎟

⎠

⎞

⎜

⎝

⎛

256

(19)

where:

KMantissa is the loop gain mantissa. Values can range from 0 to 63.

KExponent is the loop gain exponent. Values can range from 0 to 7.

As the loop gain value increases, the speed of the response of

the AGC loop increases; as the loop gain value decreases, so

does the speed of the response of the AGC loop. The slow loop

attempts to maintain the signal entering the ADC at a given

level, referred to as the requested level. This level is specified in

dBFS and can be between 0 dBFS and −24 dBFS (in 0.094 dB

steps) of the converter resolution. The default value is −6.02 dBFS.

The slow loop has a peak detection function, the period of

which can be set by the user. This period should be set to ¼ of

the symbol period, or greater, to prevent the AGC loop from

gaining off the envelope of the EDGE signal. This detection

period works because the peak detector’s operation is based on

dB (max(|I|, |Q|)); therefore, all of the I/Q samples are reflected

back into one quadrant of the I/Q plane. At a 26 MHz sampling

frequency, one symbol period is 96 clock cycles. Therefore, to

obtain a peak detector period that is ¼ of the symbol period,

the peak detector period should be set to a minimum of 24

samples. The following equation can also be used:

(

)

SYM

SAMP

Samples

Peak

SPB

≥

(20)

where:

fSYM = 270.833 kHz (GSM symbol rate).

fSAMP = 26 MHz.

Fast Attack (FA) Loop

The FA loop utilizes an analog threshold detector that prevents

overdrive of the analog signal path. In a situation that could

potentially overdrive the ADC, the FA loop takes over from the

slow loop and decreases the gain to the VGA in the front end.

The step size used for the FA loop is programmable between

0 dB and 1.504 dB in 0.094 dB steps. The FA loop also has a

counter that is programmable between 1 and 16. When

initialized to count + 1, the FA loop decreases the gain for

count + 1 clock cycles when the threshold is crossed.

Fast Decay (FD) Loop

The FD loop is a fast loop that increases the gain when the

signal falls below a threshold during a deep channel fade or on

the ramp down. The fast loop accomplishes this task by

comparing the peak signal-plus-blocker level at the ADC output

(which includes the signal and any blockers that pass through

the SAW filter) with a programmable level (SPB_level) that

determines when this loop is activated. The SBP_level default

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