AD9954SLASHPCBZ1 datasheet(9/40 Pages) AD

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AD9954

Rev. B | Page 9 of 40

Pin No.

Mnemonic

I/O

Description

COMP_IN

Comparator Complementary Input.

PWRDWNCTL

Input Pin Used as an External Power-Down Control (see Table 9 for details).

RESET

Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9954 to the default

state, as described in the right-hand column of Table 12, which is the I/O port register map.

IOSYNC

Asynchronous Active High Reset of the Serial Port Controller. When high, the current I/O

operation is immediately terminated, enabling a new I/O operation to commence once

IOSYNC is returned low. If unused, ground this pin; do not allow this pin to float.

SDO

See Serial Interface Port Pin Description section for details.

SCLK

See Serial Interface Port Pin Description section for details.

SDIO

I/O

See Serial Interface Port Pin Description section for details.

DVDD_I/O

Digital Power Supply. This pin is for I/O cells only, 3.3 V.

SYNC_IN

Input Signal Used to Synchronize Multiple AD9954s. This input is connected to the SYNC_CLK

output of a master AD9954.

SYNC_CLK

Clock Output Pin that Serves as a Synchronizer for External Hardware.

OSK

Input Pin Used to Control the Direction of the Shaped On-Off Keying Function When Programmed

for Operation. OSK is synchronous to the SYNC_CLK pin. When OSK is disabled, this pin should

be tied to DGND.

47, 48

PS0, PS1

Input Pins Used to Select One of the Internal Phase/Frequency Profiles. PS1 and PS0 are

synchronous to the SYNC_CLK pin. Change on these pins triggers a transfer of the contents of

the chosen internal buffer memory to the I/O registers (sends an internal I/O UPDATE).

<49>

AGND

The Exposed Paddle on the Bottom of the Package. It is a ground connection for the DAC and

must be attached to AGND in any board layout.

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AD9954/PCBZ1 数据表(PDF) 9 Page - Analog Devices

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