AD9954SLASHPCBZ1 datasheet(24/40 Pages) AD

24 / 40 page

AD9954

Rev. B | Page 24 of 40

DO 5 DO 4 DO 3 DO 2 DO 1 DO 0

DO 7 DO 6

INSTRUCTION CYCLE

SCLK

SDIO

DATA TRANSFER CYCLE

Figure 28. 2-Wire Serial Port Read Timing—Clock Stall High

SERIAL INTERFACE PORT PIN DESCRIPTIONS

SCLK—Serial Clock. The serial clock pin is used to synchronize

data to and from the AD9954 and to run internal state machines.

SCLK maximum frequency is 25 MHz.

CS—Chip Select. CS is an active low input that enables

devices sharing a serial communications line to be individually

programmed. The SDO and SDIO pins go to a high impedance

state when this input is high. If driven high during any

communications cycle, that cycle is suspended until CS is

reactivated low. Chip select can be tied low if it is not needed.

SDIO —Serial Data I/O. Data written to the AD9954 must be

sent to this pin. However, this pin can be used as a bidirectional

data line. CFR1<9> controls the configuration of this pin.

SDO—Serial Data Out. Data is read from this pin for protocols

that use separate lines for transmitting and receiving data.

When in 2-wire serial programming mode, this pin is set to a

high impedance state.

IOSYNC—synchronizes the I/O port state machines without

affecting the addressable registers contents. An active high input

on the IOSYNC pin aborts the current communication cycle. After

IOSYNC returns low (Logic 0), another communication cycle may

begin, starting with the instruction byte write.

MSB/LSB TRANSFERS

The AD9954 serial port can support either MSB first or LSB

first data formats. This functionality is controlled by the LSB

First Bit CFR1<8>.

For MSB first operation, the serial port controller generates the

most significant byte (of the specified register) address first

followed by the next lesser significant byte addresses until the

I/O operation is complete. All data written to (read from) the

AD9954 must be in MSB first order.

If the LSB mode is active, the serial port controller generates the

least significant byte address first followed by the next greater

significant byte addresses until the I/O operation is complete.

All data written to (read from) the AD9954 must be in LSB

first order.

Example Operation

As an example, consider the case of writing the amplitude scale

factor (ASF) register to a value of 0.5 full scale. First, calculate

the binary equivalent of 0.5. As the ASF is 16 bits wide, the

hexadecimal equivalent is 0x80. Next, for MSB first format,

transmit an instruction byte of 0x02 (serial address of ASF is

00010(b)). From this instruction, the internal controller polls

the register at this memory location and notes that the ASF is

2 bytes wide. The serial port controller’s state machines sets to

16 and awaits 16 rising edges on the SCLK and 16 bits of data

on the SDIO line. Send 16 rising edges on SCLK, and the binary

data 10000000 00000000 on the SDIO line.

To write the amplitude scale factor register in LSB first format,

the process is the same as in MSB first; however, the data is bit

wise inverted on a word-by-word basis. The instruction byte is

0x40. The binary data for the ASF is 00000000 00000001.

● ● ●

SCLK

SDIO

TCSU

TDSU

TDH

DVDD I/O = 3.3V

TCSU = 3ns

TDSU = 3ns

TDH = 0ns

DVDD I/O = 1.8V

TCSU = 5ns

TDSU = 5ns

TDH = 0ns

Figure 29. Timing Diagram for Data Write to AD9954

TDV = 25ns

SCLK

SDIO

SDO

Figure 30. Timing Diagram for Data Read to AD9954

RAM I/O VIA SERIAL PORT

Accessing the RAM via the serial port is identical to any other

serial I/O operation except that the number of bytes transferred

is determined by the address space between the beginning

address and the final address as specified in the current RAM

segment control word (RSCW). The final address describes the

most significant word address for all I/O transfers and the

beginning address specifies the least significant address.

RAM I/O supports MSB/LSB first operation as set using the

LSB First Bit CFR1<8>. When in MSB first mode, the first data

byte is for the most significant byte of the memory address

described by the final address with the remaining three bytes

making up the lesser significant bytes of that address. The

remaining bytes come in most significant to least significant,

destined for RAM addresses generated in descending order

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