AD9954SLASHPCBZ1 datasheet(16/40 Pages) AD

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AD9954

Rev. B | Page 16 of 40

Manual Shaped On-Off Keying Mode Operation

When configured for manual shaped on-off keying, the

content of the ASFR sets the scale factor for the data path.

MODES OF OPERATION

Single-Tone Mode

In single-tone mode, the DDS core uses a static tuning word.

Whatever value is stored in FTW0 is supplied to the phase

accumulator. This value can only be changed manually by

writing a new value to FTW0 and then by issuing an I/O update.

Phase adjustments are made using the phase offset register.

RAM-Controlled Modes of Operation

Three important points apply to the RAM-controlled modes:

 The user must ensure that the beginning address is lower

than the final address.

 Changing profiles or issuing an I/O update automatically

terminates the current sweep and starts the next sweep, unless

otherwise stated.

 Setting the RAM destination bit true such that the RAM

output drives the phase offset adder is valid. While the

sections that follow describe frequency sweeps, phase

sweep operation is also available. The RAM destination bit

(CFR1<30>) controls whether the RAM output drives the

phase accumulator (frequency) or the phase offset adder

(phase).

The AD9954 offers five modes of RAM-controlled operation

(see Table 7).

Table 7. RAM Modes of Operation

RSCW<7:5> (Binary)

Mode

Notes

000

Direct Switch

No sweeping, profiles

valid, no dwell ignored

001

Ramp Up

Sweeping, profiles valid,

no-dwell valid

010

Bidirectional

Ramp

Sweeping, PS0 is a

direction control pin,

no-dwell ignored

011

Continuous

Bidirectional

Ramp

Sweeping, profiles valid,

no-dwell ignored

100

Continuous

Recirculation

Sweeping, profiles valid,

no-dwell ignored

101, 110, 111

Invalid mode

Default to direct switch

Direct Switch Mode

Direct switch mode enables frequency shift keying (FSK) or

phase shift keying (PSK) modulation. The AD9954 is

programmed for direct switch using the RAM enable bit

(CFR1<31>) and programming the RAM segment mode

control bits of each desired profile to 000(b). This mode simply

reads the RAM contents at the RAM segment beginning

address for the current profile. No address ramping occurs in

this mode.

To perform 4-tone shift keying, the user programs each RAM

segment control word for direct switch mode and a unique

beginning address value. Program the RAM enable and RAM

destination bits (CFR1<31:30>) to enable the RAM and direct

the RAM output to be the FTW (FSK) or the POW (PSK). The

PS1 and PS0 inputs are the 4-tone FSK/PSK data inputs. When

the profile is changed, the data stored at the new profile is

loaded into either the phase accumulator (FSK) or the phase

offset adder (PSK). When set for PSK, Bits<17:0> of the RAM

output are unused when the RAM destination bit is set. Two-

tone shift keying only uses one profile pin.

Ramp-Up Mode

Ramp-up mode, in conjunction with the segmented RAM

capability, allows up to four different sweep profiles to be

programmed into the AD9954. The AD9954 is programmed

for ramp-up mode by enabling the RAM using the RAM enable

bit (CFR1<31>) and programming the RAM mode control bits

of each profile to be used to 001(b).

When a sweep is initiated (via an I/O update or change in

profile bits), the RAM address generator loads the RAM

segment beginning address bits of the current RSCW, driving

the RAM output from this address, and the ramp rate timer

loads the RAM segment address ramp rate bits. When the ramp

rate timer finishes a cycle, the RAM address generator increments

to the next address, the timer reloads the ramp rate bits and

begins a new countdown cycle. This sequence continues until

the RAM address generator has incremented to an address

equal to the RAM segment final address bits of the current

RSCW. At this point, the next state is dependent upon whether

no-dwell mode is active. See the no-dwell bit (CFR1<2>) in the

In this mode, asymmetrical FSK modulation can be implemented

by configuring the RAM for two segments, and using the PS0

pin as the data input.

Bidirectional Ramp Mode

Bidirectional ramp mode allows the AD9954 to offer a

symmetrical sweep between two frequencies using the PS0

signal as the control input. The AD9954 is programmed for

bidirectional ramp mode using the RAM enable bit (CFR1<31>)

and programming the RAM segment mode control bits of each

desired profile to 010(b). PS1 input is ignored; the PS0 input is

the ramp direction indicator. The memory is not segmented,

using only one beginning and one final address. The address

registers for controlling RAM are located in the RAM segment

control word (RSCW) associated with Profile 0.

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