ADE7753ARSRL datasheet(16/60 Pages) AD

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ADE7753

Rev. C | Page 16 of 60

THEORY OF OPERATION

ANALOG INPUTS

The ADE7753 has two fully differential voltage input channels.

The maximum differential input voltage for input pairs V1P/V1N

and V2P/V2N is ±0.5 V. In addition, the maximum signal level

on analog inputs for V1P/V1N and V2P/ V2N is ±0.5 V with

respect to AGND.

Each analog input channel has a programmable gain amplifier

(PGA) with possible gain selections of 1, 2, 4, 8, and 16. The

gain selections are made by writing to the gain register—see

Figure 32. Bits 0 to 2 select the gain for the PGA in Channel 1,

and the gain selection for the PGA in Channel 2 is made via

Bits 5 to 7. Figure 31 shows how a gain selection for Channel 1

is made using the gain register.

V1P

V1N

VIN

× V

GAIN[7:0]

210

000

GAIN (K)

SELECTION

OFFSET ADJUST

(±50mV)

CH1OS[7:0]

BITS 0 to 5: SIGN MAGNITUDE CODED OFFSET CORRECTION

BIT 6: NOT USED

BIT 7: DIGITAL INTEGRATOR (ON = 1, OFF = 0; DEFAULT OFF)

02875-0-031

Figure 31. PGA in Channel 1

In addition to the PGA, Channel 1 also has a full-scale input

range selection for the ADC. The ADC analog input range

selection is also made using the gain register—see Figure 32. As

mentioned previously, the maximum differential input voltage

is 0.5 V. However, by using Bits 3 and 4 in the gain register, the

maximum ADC input voltage can be set to 0.5 V, 0.25 V, or

0.125 V. This is achieved by adjusting the ADC reference—see

the ADE7753 Reference Circuit section. Table 5 summarizes the

maximum differential input signal level on Channel 1 for the

various ADC range and gain selections.

Table 5. Maximum Input Signal Levels for Channel 1

Max Signal

ADC Input Range Selection

Channel 1

0.5 V

0.25 V

0.125 V

0.5 V

Gain = 1

−

0.25 V

Gain = 2

Gain = 1

−

0.125 V

Gain = 4

Gain = 2

Gain = 1

0.0625 V

Gain = 8

Gain = 4

Gain = 2

0.0313 V

Gain = 16

Gain = 8

Gain = 4

0.0156 V

−

Gain = 16

Gain = 8

0.00781 V

−

Gain = 16

GAIN REGISTER*

CHANNEL 1 AND CHANNEL 2 PGA CONTROL

ADDR:

0x0F

* REGISTER CONTENTS

SHOW POWER-ON DEFAULTS

PGA 2 GAIN SELECT

000 = × 1

001 = × 2

010 = × 4

011 = × 8

100 = × 16

PGA 1 GAIN SELECT

000 = × 1

001 = × 2

010 = × 4

011 = × 8

100 = × 16

CHANNEL 1 FULL-SCALE SELECT

00 = 0.5V

01 = 0.25V

10 = 0.125V

02875-0-032

Figure 32. ADE7753 Analog Gain Register

It is also possible to adjust offset errors on Channel 1 and

Channel 2 by writing to the offset correction registers, CH1OS

and CH2OS, respectively. These registers allow channel offsets

in the range ±20 mV to ±50 mV (depending on the gain setting)

to be removed. Channel 1 and 2 offset registers are sign magni-

tude coded. A negative number is applied to the Channel 1

offset register, CH1OS, for a negative offset adjustment. Note

that the Channel 2 offset register is inverted. A negative number

is applied to CH2OS for a positive offset adjustment. It is not

necessary to perform an offset correction in an energy measure-

ment application if HPF in Channel 1 is switched on. Figure 33

shows the effect of offsets on the real power calculation. As seen

from Figure 33, an offset on Channel 1 and Channel 2

contributes a dc component after multiplication. Because this dc

component is extracted by LPF2 to generate the active (real)

power information, the offsets contribute an error to the active

power calculation. This problem is easily avoided by enabling

HPF in Channel 1. By removing the offset from at least one

channel, no error component is generated at dc by the

multiplication. Error terms at cos(ωt) are removed by LPF2 and

by integration of the active power signal in the active energy

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