MCP795W21 datasheet(16/54 Pages) MICROCHIP

16 / 54 page

MCP795W1X/MCP795W2X

DS22280C-page 16

Preliminary

 2011-2012 Microchip Technology Inc.

WATCHDOG 0X0A

R/W

WDTEN

WDTIF

WDDEL

WDTPLS

WD3

WD2

WD1

WD0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

bit 7

WDTEN: Watchdog Timer Enable bit

This bit is a read/write bit that is set by the user and can be cleared by the user of the hardware. This

bit is set to enable the WDT function and cleared to disable the function. This bit is cleared by the

hardware when the VCC supply is not present, it is not set again when VCC is present.

bit 6

WDTIF: Watchdog Timer Interrupt Flag bit

This bit is a read/write bit that is set in hardware when the WDT times out and the WD pin is asserted.

This bit must be cleared in software to restart the WDT.

bit 5

WDDEL: Watchdog Timer Delay bit

This bit is a read/write bit and is set to enable a 64-second delay before the WDT starts to count. If

this bit is set and the WDTIF bit is cleared then there will be a 64 second delay before the WDT starts

to count. This bit should be set before the WDTEN bit is set.

bit 4

WDTPLS: Watchdog Timer Reset Pulse Width bit

A read/write bit that is used to select the pulse width on the WD pin when the WDT times out.

- 0 – 122 us Pulse

- 1 – 125 ms Pulse

bit 3-0

WD<3:0>: Watchdog Timer Configuration bits

Read/write bits that are used to set the WDT time-out period as below (all times are based off the

uncalibrated crystal reference). Bit 3 should be cleared and is reserved for future use:

- 000 – 977 us

- 001 – 15.6 ms

- 010 – 62.5 ms

- 011 – 125 ms

- 100 – 1s

- 101 – 16s

- 110 – 32s

- 111 – 64s

Note 1:

Please see Section 9.1.3, Watchdog Timer for more information.

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