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MCP795W21 数据表(PDF) 17 Page - Microchip Technology

部件名 MCP795W21
功能描述  3V SPI Real-Time Clock Calendar with Enhanced Features and Battery Switchover
PDF  54 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

MCP795W21 数据表(HTML) 17 Page - Microchip Technology

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 2011-2012 Microchip Technology Inc.
Preliminary
DS22280C-page 17
MCP795W1X/MCP795W2X
REGISTER 5-12:
EVENT DETECT 0X0B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EVHIF
EVLIF
EVEN1
EVEN0
EVWDT
EVLDB
EVHS1
EVHS0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
bit 7
EVHIF: High-Speed Event Interrupt Flag bit
When the configured number of high-speed events has occurred, the IRQ pin is asserted and the
EVHIF bit is set in hardware. To clear the interrupt and the IRQ pin the EVHIF bit must be cleared in
software.
bit 6
EVLIF: Low-Speed Event Interrupt Flag bit
When an event occurs on the low-speed pin, this IRQ pin is asserted and the EVLIF bit is set. This bit
must be cleared by software to reset the module and clear the IRQ pin.
bit 5:4
EVEN<1:0>: Event Detect Configuration bits
These two bits determine what combination of the high and low-speed modules are enabled.
- 00 – Both modules are Off
- 01 – Low-speed module enabled, high speed disabled
- 10 – Low-speed module disabled, high speed enabled
- 11 – Both modules are enabled
bit 3
EVWDT: EVHS Watchdog Timer Reset Enable bit
Setting this bit overrides any setting for the High-Speed Event Detection and allows the EVHS pin to
clear the Watchdog Timer. This is edge triggered. Either an H-L or L-H transition will clear the WDT.
bit 2
EVLDB: Low-Speed Event Detect Debounce Configuration bit
This is the Low-Speed Event Debounce setting. Depending on the state of this bit, the low-speed pin
will have to remain at the same state for the following periods to be considered valid.
- 0 – 31.25 ms
- 1 – 500 ms
bit 1-0
EVHS<1:0>: High-Speed Event Detect Configuration bits
Determines how many high-speed events must occur before the EVHIF bit is set.
All of these events must occur within 250 ms (based on the uncalibrated 32.768 kHz clock).
- 00 – 1st Event
- 01 – 4th Event
- 10 – 16th Event
- 11 – 32nd Event
Note 1:
Please see Section 9.1.4, Event Detection for more information.



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