STM32L152C6 datasheet(93/121 Pages) STMICROELECTRONICS

93 / 121 page

STM32L151x6/8/B, STM32L152x6/8/B

Electrical characteristics

Doc ID 17659 Rev 8

93/121

Figure 25.

ADC accuracy characteristics

Figure 26.

Typical connection diagram using the ADC

Refer to Table 56: RAIN max for fADC = 16 MHz for the value of RAIN and Table 54: ADC characteristics for

the value of CADC

Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy

this, fADC should be reduced.

1LSBIDEAL

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

ET=Total Unadjusted Error: maximum deviation

between the actual and the ideal transfer curves.

EO=Offset Error: deviation between the first actual

transition and the first ideal one.

EG=Gain Error: deviation between the last ideal

transition and the last actual one.

ED=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.

EL=Integral Linearity Error: maximum deviation

between any actual transition and the end point

correlation line.

4095

4094

4093

456

4093 4094 4095 4096

(1)

(2)

(3)

VDDA

VSSA

ai14395b

VREF+

4096

(or

depending on package)]

VDDA

4096

[1LSBIDEAL =

ai17856c

STM32L15xxx

VDD

AINx

IL± 50 nA

0.6 V

RAIN(1)

C parasitic

VAIN

0.6 V

12-bit

converter

CADC(1)

Sample and hold ADC

converter

STM32L152C6 数据表(PDF) 93 Page - STMicroelectronics

STM32L152C6 数据表(HTML) 93 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载