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STM32L152C6 数据表(PDF) 94 Page - STMicroelectronics |
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STM32L152C6 数据表(HTML) 94 Page - STMicroelectronics |
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94 / 121 page  Electrical characteristics STM32L151x6/8/B, STM32L152x6/8/B 94/121 Doc ID 17659 Rev 8 Figure 27. Maximum dynamic current consumption on VREF+ supply pin during ADC conversion General PCB design guidelines Power supply decoupling should be performed as shown in Figure 28 or Figure 29, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip. ADC clock Sampling (n cycles) Conversion (12 cycles) Iref+ 300µA 700µA Table 56. RAIN max for fADC = 16 MHz (1) Ts (cycles) Ts (µs) RAIN max (kohm) Multiplexed channels Direct channels 2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA < 3.3 V 1.8 V < VDDA < 2.4 V 4 0.25 Not allowed Not allowed 0.7 Not allowed 9 0.5625 0.8 Not allowed 2.0 1.0 16 1 2.0 0.8 4.0 3.0 24 1.5 3.0 1.8 6.0 4.5 48 3 6.8 4.0 15.0 10.0 96 6 15.0 10.0 30.0 20.0 192 12 32.0 25.0 50.0 40.0 384 24 50.0 50.0 50.0 50.0 1. Guaranteed by design, not tested in production. |
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