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OMAP3530ECBBA 数据表(PDF) 250 Page - Texas Instruments |
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OMAP3530ECBBA 数据表(HTML) 250 Page - Texas Instruments |
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250 / 264 page  sdti_clk sdti_txd[3:0] Header Header Ad[7:4] Ad[3:0] Da[15:12] Da[11:8] Da[7:4] Da[3:0] SD1 SD2 SD3 SD3 030-111 6.8.2.2 System Debug Trace Interface in Single-Edge Mode OMAP3530/25 Applications Processor SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 www.ti.com Table 6-143. System Debug Trace Interface Timing Conditions – Dual-Edge Mode TIMING CONDITION PARAMETER VALUE UNIT Output Conditions CLOAD Output load capacitance 25 pF Table 6-144. System Debug Trace Interface Switching Characteristics – Dual-Edge Mode NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX SD1 tc(CLK) Cycle time, sdti_clk period 29 29 ns SD2 tw(CLK) Typical pulse duration, sdti_clk high or low 0.5*P(1) 0.5*P(1) ns tdc(CLK) Duty cycle error, sdti_clk –1.2 1.2 –1.2 1.2 ns tR(CLK) Rise time, sdti_clk 5 5 ns tF(CLK) Fall time, sdti_clk 5 5 ns SD3 td(CLK-TxD) Delay time, sdti_clk Multiplexing mode on etk pins 2.3 10.9 2.3 10.9 ns transition to sdti_txd[3:0] Multiplexing mode on 2.3 13.9 2.3 13.9 transition jtag_emu pins tR(CLK) Rise time, sdti_txd[3:0] 5 5 ns tF(CLK) Fall time, sdti_txd[3:0] 5 5 ns (1) P = sdti_clk clock period Figure 6-70. System Debug Trace Interface – Dual-Edge Mode Table 6-146 assumes testing over the recommended operating conditions and electrical characteristic conditions (see Figure 6-71). Table 6-145. System Debug Trace Interface Timing Conditions – Single-Edge Mode TIMING CONDITION PARAMETER VALUE UNIT Output Conditions CLOAD Output load capacitance 25 pF Table 6-146. System Debug Trace Interface Switching Characteristics – Single-Edge Mode NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX SD1 tc(CLK) Cycle time, sdti_clk period 29 29 ns SD2 tw(CLK) Typical pulse duration, sdti_clk high or low 0.5*P(1) 0.5*P(1) ns tdc(CLK) Duty cycle error, sdti_clk –1.2 1.2 –1.2 1.2 ns tR(CLK) Rise time, sdti_clk 5 5 ns tF(CLK) Fall time, sdti_clk 5 5 ns SD3 td(CLK-TxD) Delay time, sdti_clk Multiplexing mode on etk pins 2.3 26.5 2.3 26.5 ns transition to sdti_txd[3:0] Multiplexing mode on jtag_emu 2.3 33.2 2.3 33.2 transition pins tR(CLK) Rise time, sdti_txd[3:0] 5 5 ns (1) P = sdti_clk clock period. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 250 Submit Documentation Feedback |
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