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OMAP3530ECBBA 数据表(PDF) 95 Page - Texas Instruments |
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OMAP3530ECBBA 数据表(HTML) 95 Page - Texas Instruments |
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95 / 264 page  OMAP3530/25 Applications Processor www.ti.com SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 Table 2-5. External Memory Interfaces – GPMC Signals Description (continued) SIGNAL NAME DESCRIPTION [2] TYPE BALL BALL BALL BOTTOM BALL TOP BALL SUBSYSTEM [1] [3] BOTTOM TOP (CBC Pkg.) [4] (CBC Pkg.) [5] BOTTOM PIN (CBB (CBB (CUS MULTIPLEXING Pkg.) [4] Pkg.) [5] Pkg.) [4] [6] gpmc_a17 General-purpose memory address O N4 AC15 J2 NA K4 gpmc_a1 bit 17 gpmc_a18 General-purpose memory address O M4 AB15 H1 NA K3 gpmc_a2 bit 18 gpmc_a19 General-purpose memory address O L4 AC16 H2 NA K2 gpmc_a3 bit 19 gpmc_a20 General-purpose memory address O K4 AB16 G2 NA J4 gpmc_a4 bit 20 gpmc_a21 General-purpose memory address O T3 AC17 F1 NA J3 gpmc_a5 bit 21 gpmc_a22 General-purpose memory address O R3 AB17 F2 NA J2 gpmc_a6 bit 22 gpmc_a23 General-purpose memory address O N3 AC18 E1 NA J1 gpmc_a7 bit 23 gpmc_a24 General-purpose memory address O M3 AB18 E2 NA H1 gpmc_a8 bit 24 gpmc_a25 General-purpose memory address O L3 AC19 D1 NA H2 gpmc_a9 bit 25 gpmc_a26 General-purpose memory address O K3 AB19 D2 NA G2 gpmc_a10 bit 26 gpmc_d0 GPMC Data bit 0 IO K1 M2 AA2 U2 L2 gpmc_a1/ gpmc_d0 gpmc_d1 GPMC Data bit 1 IO L1 M1 AA1 U1 M1 gpmc_a2/ gpmc_d1 gpmc_d2 GPMC Data bit 2 IO L2 N2 AC2 V2 M2 gpmc_a3/ gpmc_d2 gpmc_d3 GPMC Data bit 3 IO P2 N1 AC1 V1 N2 gpmc_a4/ gpmc_d3 gpmc_d4 GPMC Data bit 4 IO T1 R2 AE5 AA3 M3 gpmc_a5/ gpmc_d4 gpmc_d5 GPMC Data bit 5 IO V1 R1 AD6 AA4 P1 gpmc_a6/ gpmc_d5 gpmc_d6 GPMC Data bit 6 IO V2 T2 AD5 Y3 P2 gpmc_a7 /gpmc_d6 gpmc_d7 GPMC Data bit 7 IO W2 T1 AC5 Y4 R1 gpmc_a8/ gpmc_d7 gpmc_d8 GPMC Data bit 8 IO H2 AB3 V1 R1 R2 gpmc_a9/ gpmc_d8 gpmc_d9 GPMC Data bit 9 IO K2 AC3 Y1 T1 T2 gpmc_a10/ gpmc_d9 gpmc_d10 GPMC Data bit 10 IO P1 AB4 T1 N1 U1 gpmc_a11/ gpmc_d10 gpmc_d11 GPMC Data bit 11 IO R1 AC4 U2 P2 R3 gpmc_a12/ gpmc_d11 gpmc_d12 GPMC Data bit 12 IO R2 AB6 U1 P1 T3 gpmc_a13/ gpmc_d12 gpmc_d13 GPMC Data bit 13 IO T2 AC6 P1 M1 U2 gpmc_a14/ gpmc_d13 gpmc_d14 GPMC Data bit 14 IO W1 AB7 L2 J2 V1 gpmc_a15/ gpmc_d14 gpmc_d15 GPMC Data bit 15 IO Y1 AC7 M2 K2 V2 gpmc_a16/ gpmc_d15 gpmc_ncs0 GPMC Chip Select bit 0 O G4 Y2 AD8 AA8 E2 NA gpmc_ncs1 GPMC Chip Select bit 1 O H3 Y1 AD1 W1 NA NA gpmc_ncs2 GPMC Chip Select bit 2 O V8 NA A3 NA NA NA gpmc_ncs3 GPMC Chip Select bit 3 O U8 NA B6 NA D2 NA gpmc_ncs4 GPMC Chip Select bit 4 O T8 NA B4 NA F4 NA gpmc_ncs5 GPMC Chip Select bit 5 O R8 NA C4 NA G5 NA Submit Documentation Feedback TERMINAL DESCRIPTION 95 |
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