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OMAP3530ECBBA 数据表(PDF) 48 Page - Texas Instruments |
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OMAP3530ECBBA 数据表(HTML) 48 Page - Texas Instruments |
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48 / 264 page  OMAP3530/25 Applications Processor SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 www.ti.com Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BALL BUFFER PULLUP BALL BALL TOP PIN NAME RESET REL. MODE [4] TYPE [5] RESET RESET REL. POWER [9] HYS [10] STRENG TH /DOWN IO CELL [13] BOTTOM [1] [2] [3] MODE [8] STATE [6] STATE [7] (mA) [11] TYPE [12] NA AA18 sdrc_ba0 0 O 0 0 0 vdds No 4 (2) NA LVCMOS NA V20 sdrc_ba1 0 O 0 0 0 vdds No 4 (2) NA LVCMOS NA Y15 sdrc_cke0 0 O H 1 7 vdds Yes 4 (2) PU100/ LVCMOS PD100 safe_mode 7 NA Y13 sdrc_cke1 0 O H 1 7 vdds Yes 4 (2) PU100/ LVCMOS PD100 safe_mode 7 NA A12 sdrc_clk 0 IO L 0 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA D1 sdrc_d0 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA G1 sdrc_d1 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA G2 sdrc_d2 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA E1 sdrc_d3 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA D2 sdrc_d4 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA E2 sdrc_d5 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA B3 sdrc_d6 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA B4 sdrc_d7 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA A10 sdrc_d8 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA B11 sdrc_d9 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA A11 sdrc_d10 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA B12 sdrc_d11 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA A16 sdrc_d12 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA A17 sdrc_d13 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA B17 sdrc_d14 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA B18 sdrc_d15 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA B7 sdrc_d16 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA A5 sdrc_d17 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA B6 sdrc_d18 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA A6 sdrc_d19 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA A8 sdrc_d20 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA B9 sdrc_d21 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA A9 sdrc_d22 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA B10 sdrc_d23 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA C21 sdrc_d24 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA D20 sdrc_d25 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA B19 sdrc_d26 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 NA C20 sdrc_d27 0 IO L Z 0 vdds Yes 4 (2) PU100/ LVCMOS PD100 TERMINAL DESCRIPTION 48 Submit Documentation Feedback |
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