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OMAP3530ECBBA 数据表(PDF) 47 Page - Texas Instruments

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部件名 OMAP3530ECBBA
功能描述  OMAP3530/25 Applications Processor: OMAP 3 Architecture
PDF  264 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECBBA 数据表(HTML) 47 Page - Texas Instruments

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OMAP3530/25 Applications Processor
www.ti.com
SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009
Table 2-1. Ball Characteristics (CBB Pkg.) (continued)
BALL
BALL TOP
PIN NAME
MODE [4]
TYPE [5]
BALL
BALL
RESET REL. POWER [9]
HYS [10]
BUFFER
PULLUP
IO CELL [13]
BOTTOM [1] [2]
[3]
RESET
RESET REL. MODE [8]
STRENG TH /DOWN
STATE [6]
STATE [7]
(mA) [11]
TYPE [12]
AH1, AH2,
A2, A12,
FeedThrough -
-
-
-
-
-
-
-
-
-
AH10, AH11, A22, A23,
Pins
(5)
AH13, AH15, AA1, AA2,
AH16, AH27, AA22, AA23,
AH28, AG1,
AB1, AB11,
AG10, AG11, AB13, AB23,
AG13, AG15, AB8, AB9,
AG28, AF1,
AC1, AC11,
AF2, AF27,
AC13, AC14,
AF28, AE28, AC2, AC22,
AA1, AA2,
AC23, AC8,
N1, N2, M1,
AC9, B12,
M2, M26,
B23, H22,
J27, J28,
H23, K1, K2,
B15, B28,
K22, L1, L2,
A2, A15,
U1, U2, Y23
A27, A28
A1, B1, G1,
A1, AB2,
No Connect
-
-
U4
AB22, B1,
B2, B22
(5)
These signals are feed-through balls. For more information, see Section 2.5.10.
Table 2-2. Ball Characteristics (CBC Pkg.)(1)
BALL
BALL
BUFFER
PULLUP
BALL
BALL TOP
PIN NAME
RESET REL.
MODE [4]
TYPE [5]
RESET
RESET REL.
POWER [9]
HYS [10]
STRENG TH
/DOWN
IO CELL [13]
BOTTOM [1]
[2]
[3]
MODE [8]
STATE [6]
STATE [7]
(mA) [11]
TYPE [12]
AE16
NA
cam_d0
0
I
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_99
4
I
safe_mode
7
-
AE15
NA
cam_d1
0
I
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_100
4
I
safe_mode
7
-
AD17
NA
gpio_112
4
I
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
safe_mode
7
-
AE18
NA
gpio_114
4
I
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
safe_mode
7
-
AD16
NA
gpio_113
4
I
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
safe_mode
7
-
AE17
NA
gpio_115
4
I
L
L
7
vdds
Yes
4
PU100/
LVCMOS
PD100
safe_mode
7
-
NA
G20
sdrc_a0
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
K20
sdrc_a1
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
J20
sdrc_a2
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
J21
sdrc_a3
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
U21
sdrc_a4
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
R20
sdrc_a5
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
M21
sdrc_a6
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
M20
sdrc_a7
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
N20
sdrc_a8
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
K21
sdrc_a9
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
Y16
sdrc_a10
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
N21
sdrc_a11
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
R21
sdrc_a12
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
AA15
sdrc_a13
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
NA
Y12
sdrc_a14
0
O
0
0
0
vdds
No
4
(2)
NA
LVCMOS
(1)
NA in this table stands for Not Applicable.
(2)
The drive strength is programmable vs the capacity load: load range = [2 pF to 6 pF] per default or [6 pF to 12 pF] according to the
selected mode.
Submit Documentation Feedback
TERMINAL DESCRIPTION
47



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