OMAP3530ECBBA datasheet(130/264 Pages) TI1

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3.6 Power-up and Power-down

3.6.1

Power-up Sequence

OMAP3530/25 Applications Processor

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

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This section provides the timing requirements for the OMAP3530/25 hardware signals.

The following steps give an example of power-up sequence supported by the OMAP3530/25 device.

1. vdds and vdds_mem are ramped ensuring a level on the IO domain and sys_nrespwron must be low.

At the same time, vdds_sram and vdds_wkup_bg can also be ramped.

2. Once vdds_wkup_bg rail is stabilized, vdd_core can be ramped.

3. Once vdd_core is stabilized, then vdd_mpu_iva can be ramped.

4. vdds_dpll_dll and vdds_dpll_per rails can be ramped at any time during the above sequence.

5. sys_nrespwron can be released as soon as the vdds_pll_dll rail is stabilized, and sys_xtalin and

sys_32k clocks are stabilized.

6. During the whole sequence above, sys_nreswarm is held low by OMAP3530/25. sys_nreswarm is

released after the eFuse check has been performed; that is, after sys_nrespwron is released.

7. The other power supplies can then be turned on upon software request.

shows the power-up sequence.

Notes:

• If an external square clock is provided, it could be started after sys_nrespwron release provided it is

clean: no glitch, stable frequency, and duty cycle.

• Higher voltage can be used. OPP voltage values may change following the silicon characterization

result.

130

ELECTRICAL CHARACTERISTICS

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