OMAP3530ECBBA datasheet(138/264 Pages) TI1

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sys_altclk

ALT0

ALT1

030-013

OMAP3530/25 Applications Processor

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

www.ti.com

Table 4-9. 48- or 54-MHz Input Clock Source Timing Requirements(1)(2)

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

ALT0

1 / tc(altclk)

Frequency, sys_altclk

48-, 54-, or up to 59- MHz

MHz

ALT1

tw(altclk)

Pulse duration, sys_altclk low or

0.40 * tc(altclk)

0.60 * tc(altclk)

high

ALT2

tJ(altclk)

Peak-to-peak jitter(1), sys_altclk

–1%

ALT3

tR(altclk)

Rise time, sys_altclk

ALT4

tF(altclk)

Fall time, sys_altclk

ALT5

tJ(altclk)

Frequency stability, sys_altclk

± 50

ppm

(1)

Peak-to-peak jitter is defined as the difference between the maximum and the minimum output periods on a statistical population of 300

period samples. The sinusoidal noise is added on top of the vdds supply voltage.

(2)

See Table 3-4, Electrical Characteristics, for sys_altclk VIH/VIL parameters.

Figure 4-6. Alternate CMOS Clock

138

CLOCK SPECIFICATIONS

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