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OMAP3530ECBC 数据表(PDF) 246 Page - Texas Instruments |
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OMAP3530ECBC 数据表(HTML) 246 Page - Texas Instruments |
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246 / 264 page  OMAP3530/25 Applications Processor SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 www.ti.com Table 6-138. MMC/SD/SDIO Timing Requirements – Standard SD Mode(1)(2)(3) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX Standard SD Mode MMC/SD/SDIO Interface 1 (1.8 V IO) SD3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk 6.2 47.7 ns rising clock edge SD4 tsu(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk 19.4 19.2 ns rising clock edge SD7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before mmc1_clk 6.2 47.7 ns rising clock edge SD8 tsu(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk 19.4 19.2 ns rising clock edge MMC/SD/SDIO Interface 1 (3.0 V IO) SD3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk 6.2 47.7 ns rising clock edge SD4 tsu(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk 19.4 19.2 ns rising clock edge SD7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before mmc1_clk 6.2 47.7 ns rising clock edge SD8 tsu(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk 19.4 19.2 ns rising clock edge MMC/SD/SDIO Interface 2 SD3 tsu(CMDV-CLKIH) Setup time, mmc2_cmd valid before mmc2_clk 6.2 47.7 ns rising clock edge SD4 tsu(CLKIH-CMDIV) Hold time, mmc2_cmd valid after mmc2_clk 19.4 19.2 ns rising clock edge SD7 tsu(DATxV-CLKIH) Setup time, mmc2_datx valid before mmc2_clk 6.2 47.7 ns rising clock edge SD8 tsu(CLKIH-DATxIV) Hold time, mmc2_datx valid after mmc2_clk 19.4 19.2 ns rising clock edge MMC/SD/SDIO Interface 3 SD3 tsu(CMDV-CLKIH) Setup time, mmc3_cmd valid before mmc3_clk 6.2 47.7 ns rising clock edge SD4 tsu(CLKIH-CMDIV) Hold time, mmc3_cmd valid after mmc3_clk 19.4 19.2 ns rising clock edge SD7 tsu(DATxV-CLKIH) Setup time, mmc3_datx valid before mmc3_clk 6.2 47.7 ns rising clock edge SD8 tsu(CLKIH-DATxIV) Hold time, mmc3_datx valid after mmc3_clk 19.4 19.2 ns rising clock edge (1) Timing parameters are referred to output clock specified in Table 6-139. (2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-139. (3) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7. Table 6-139. MMC/SD/SDIO Switching Characteristics – Standard SD Mode NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX Standard SD Mode 1/SD 1/tc(clk) Frequency (1), mmcx_clk(2) 24 12 MHz 1 SD2 tW(clkH) Typical pulse duration, output clk high X(3)*PO(4) X(3)*PO(4) ns (1) Related with the output clk maximum and minimum frequencies programmable in I/F module. (2) In mmcx_clk, 'x' is equal to 1, 2, or 3. (3) The X parameter is defined as shown in Table 6-140. (4) PO = output clk period in ns. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 246 Submit Documentation Feedback |
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