OMAP3530ECBC datasheet(249/264 Pages) TI1

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6.8 Test Interfaces

6.8.1

Embedded Trace Macro Interface (ETM)

etk_clk

etk_ctl

etk_d[15:0]

ETM0

ETM2

ETM3

ETM2

ETM1

ETM3

030-110

6.8.2

System Debug Trace Interface (SDTI)

6.8.2.1 System Debug Trace Interface in Dual-Edge Mode

OMAP3530/25 Applications Processor

www.ti.com

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

The emulation and trace interfaces allow tracing activities of the following CPUs:

• ARM1136JF-STM through an Embedded Trace Macro-cell (ETM11) dedicated to enable real-time

trace of the ARM subsystem operations and a Serial Debug Trace Interface (SDTI)

• IVA2 DSP through a high-speed real-time data exchange (HS-RTDX) controller

All processors can be emulated via JTAG ports.

Table 6-142 assumes testing over the recommended operating conditions (see Figure 6-69).

Table 6-142. Embedded Trace Macro Interface Switching Characteristics(1)

NO.

PARAMETER

1.15 V

UNIT

MIN

MAX

1/tc(CLK)

Frequency, etk_clk

166

MHz

ETM0

tc(CLK)

Cycle time(2), etk_clk

ETM1

tW(CLK)

Clock pulse width, etk_clk

2.7

ETM2

td(CLK-CTL)

Delay time, etk_clk clock edge to etk_ctl transition

–0.5

0.5

ETM3

td(CLK-D)

Delay time, etk_clk clock high to etk_d[15:0] transition

–0.5

0.5

(1)

The capacitive load is equivalent to 25 pF.

(2)

Cycle time is given by considering a jitter of 5%.

Figure 6-69. Embedded Trace Macro Interface

The system debug trace interface (SDTI) module provides real-time software tracing functionality to the

OMAP3530/25 device.

The trace interface has four trace data pins and a trace clock pin.

This interface is a dual-edge interface: the data are available on rising and falling edges of sdti_clk but can

be also configured in single edge mode where data are available on falling edge of sdti_clk.

Serial interface operates in clock stop regime: serial clock is not free running, when there is no trace data

there is no trace clock.

Table 6-144 assumes testing over the recommended operating conditions and electrical characteristic

conditions (see Figure 6-70).

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TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

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