OMAP3530ECBC datasheet(136/264 Pages) TI1

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sys_xtalin

sys_xtalout

OMAP Device

sys_clkreq

ClockSquarerSource

Oscillator

InBypassMode

030-010

OMAP3530/25 Applications Processor

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

www.ti.com

Figure 4-3. Clock Squarer Source Connection

To connect a digital clock source, the oscillator is configured in bypass mode(1). The sys_clkreq(2) pin is an

OMAP3530/25 output which can be used to switch the clock source on or off.

1. Pin sys_xtalout is not used in this mode. It must be left unconnected.

2. Once the system is powered up, the clock squarer source or crystal oscillator source can be applied;

however, this affects the performance. The input source must be configured after power up to attain

the desired system requirements.

Table 4-4 summarizes the electrical constraints required by the clock squarer used in the fundamental

mode of operation.

Note: There is an internal pulldown resistor of 5k

Ω (max.) on sys_xtalin when the oscillator is disabled.

Table 4-4. Base Oscillator Electrical Characteristics (in Bypass Mode)

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

Frequency(1)

12, 13, 16.8, 19.2, 26, or 38.4

MHz

tsX

Start-up time

(2)ms

IDDQ

Current consumption on VDDS when sys_xtalin = 0 and in

µA

power-down mode

(1)

Measured with the load capacitance specified by the manufacturer. Parasitic capacitance from package and board must also be taken in

account.

(2)

Before the processor boots up and the oscillator is set to bypass mode, there is a start-up time when the internal oscillator is in

application mode and receives a square wave. The start-up time in this case is about 100

µs.

Table 4-5 details the input requirements of the 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-MHz input clock.

Table 4-5. 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-MHz Input Clock Squarer Timing Requirements

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

OCS0

1 / tc(xtalin)

Frequency, sys_xtalin

12, 13, 16.8, 19.2, 26, or 38.4

MHz

OCS1

tw(xtalin)

Pulse duration, sys_xtalin low or high

0.45 * tc(xtalin)

0.55 * tc(xtalin)

OCS2

tJ(xtalin)

Peak-to-peak jitter(1), sys_xtalin

–1%

OCS3

tR(xtalin)

Rise time, sys_xtalin

3.6

OCS4

tF(xtalin)

Fall time, sys_xtalin

3.6

OCS5

tJ(xtalin)

Frequency stability, sys_xtalin

±25

ppm

(1)

Peak-to-peak jitter is defined as the difference between the maximum and the minimum output periods on a statistical population of 300

period samples. The sinusoidal noise is added on top of the vdds supply voltage.

CLOCK SPECIFICATIONS

136

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