OMAP3530ECBC datasheet(153/264 Pages) TI1

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TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

6.1 Timing Test Conditions

6.2 Interface Clock Specifications

6.2.1

Interface Clock Terminology

6.2.2

Interface Clock Frequency

6.2.3

Clock Jitter Specifications

Cycle(orPeriod)Jitter

Tn-1

Tn+1

Max.CycleJitter=Max(T )

Min.CycleJitter=Min(T )

JitterStandardDeviation(orrmsJitter)=StandardDeviation(T )

030-020

6.2.4

Clock Duty Cycle Error

OMAP3530/25 Applications Processor

www.ti.com

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

All timing requirements and switching characteristics are valid over the recommended operating conditions

of Table 3-3, unless otherwise specified.

The Interface clock is used at the system level to sequence the data and/or control transfers accordingly

with the interface protocol.

The two interface clock characteristics are:

• The maximum clock frequency

• The maximum operating frequency

The interface clock frequency documented in this document is the maximum clock frequency, which

corresponds to the maximum frequency programmable on this output clock. This frequency defines the

maximum limit supported by the OMAP3530/25 IC and doesn’t take into account any system consideration

(PCB, peripherals).

The system designer will have to consider these system considerations and OMAP3530/25 IC timings

characteristics as well, to define properly the maximum operating frequency, which corresponds to the

maximum frequency supported to transfer the data on this interface.

Jitter is a phase noise, which may alter different characteristics of a clock signal. The jitter specified in this

document is the time difference between the typical cycle period and the actual cycle period affected by

noise sources on the clock. The cycle (or period) jitter terminology identifies this type of jitter.

Figure 6-1. Cycle (or Period) Jitter

The duty cycle error is the ratio between either the high-level pulse duration or the low-level pulse duration

and the cycle time of a clock signal.

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