LSM303DLHC datasheet(33/42 Pages) STMICROELECTRONICS

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LSM303DLHC

Doc ID 018771 Rev 1

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Interrupt 2 source register. Read only register.

Reading at this address clears INT2_SRC IA bit (and the interrupt signal on the INT 2 pin)

and allows the refreshing of data in the INT2_SRC register if the latched option was chosen.

7.1.20

INT2_THS_A (36h)

7.1.21

INT2_DURATION_A (37h)

Table 53.

INT2_SRC_A description

Interrupt active. Default value: 0

(0: no interrupt has been generated, 1: one or more interrupts have been generated)

Z high. Default value: 0

(0: no interrupt, 1: Z high event has occurred)

Z low. Default value: 0

(0: no interrupt, 1: Z low event has occurred)

Y high. Default value: 0

(0: no interrupt, 1: Y high event has occurred)

Y low. Default value: 0

(0: no interrupt, 1: Y low event has occurred)

X high. Default value: 0

(0: no interrupt, 1: X high event has occurred)

X Low. Default value: 0

(0: no interrupt, 1: X low event has occurred)

Table 54.

INT2_THS_A register

0(1)

This bit must be set to ‘0’ for correct working of the device

THS6

THS5

THS4

THS3

THS2

THS1

THS0

Table 55.

INT2_THS_A description

THS6 - THS0

Interrupt 1 threshold. Default value: 000 0000

Table 56.

INT2_DURATION_A register

0(1)

This bit must be set to ‘0’ for correct working of the device

Table 57.

INT2_DURATION_A description

D6-D0

Duration value. Default value: 000 0000

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