M24C64-R datasheet(41/42 Pages) STMICROELECTRONICS

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M24C64-W M24C64-R M24C64-F M24C64-DF

Revision history

Doc ID 16891 Rev 27

41/42

16-Dec-2011

Updated A dimension in Table 22: WLCSP-R 5-bump wafer-length chip-

scale package mechanical data.

28-Aug-2012

Datasheet split into:

– M24C64-DF, M24C64-W, M24C64-R,M24C64-F (this datasheet) for

tandard products (range 6),

– M24C64-125 datasheet for automotive products (range 3).

Added 8-bump thin WLCSP.

Updated single supply voltage and number of Write cycles on cover

page.

Updated Section 2.1: Serial Clock (SCL) and Section 2.2: Serial Data

(SDA).

Updated Figure 6: Block diagram.

Added Section 4.5: Device addressing.

Section 5.1: Write operations move to Section 5: Instructions and

updated.

Moved Figure 8: Write mode sequences with WC = 0 (data write

enabled) to Section 5.1.1: Byte Write.

Section 5.1.2: Page Write: changed address bits to A15/A5 and updated

Figure 9.

Case of locked Write identification Page removed from Section 5.1.4:

Lock Identification Page (M24C64-D only).

Updated Section 5.1.5: ECC (Error Correction Code) and Write cycling

and move Figure 10: Write cycle polling flowchart using ACK to

Section 5.1.6: Minimizing Write delays by polling on ACK.

Added note 1 in Table 6: Operating conditions (voltage range W) and

Table 7: Operating conditions (voltage range R).

Added Table 11: Cycling performance by groups of four bytes and

updated Table 12: Memory cell data retention.

Removed note 2 in Table 16: 400 kHz AC characteristics for tQL1QL2,

tWLDL, tDHWH, and tNS.

Table 24: Ordering information scheme: removed ambient operating

temperature for device grade 5 and added Note 2. to MLP8 and WLCSP

packages.

Table 25.

Document revision history (continued)

Date

Revision

Changes

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