AD5665BCPZ-R2 datasheet(29/36 Pages) AD

29 / 36 page

Data Sheet

AD5625R/AD5645R/AD5665R, AD5625/AD5665

Rev. C | Page 29 of 36

Synchronous LDAC

The DAC registers are updated after new data is read in. LDAC

can be permanently low or pulsed.

Asynchronous LDAC

The outputs are not updated at the same time that the input

registers are written to. When LDAC goes low, the DAC

registers are updated with the contents of the input register.

The LDAC register gives the user full flexibility and control over

the hardware LDAC pin (and software LDAC on the 10-lead

parts that do not have the hardware LDAC pin—see Table 13).

This register allows the user to select which combination of

channels to simultaneously update when the hardware LDAC

pin is executed. Setting the LDAC bit register to 0 for a DAC

channel means that the update of this channel is controlled by

the LDAC pin. If this bit is set to 1, this channel synchronously

updates; that is, the DAC register is updated after new data is

read in, regardless of the state of the LDAC pin. The device

effectively sees the LDAC pin as being pulled low. See Table 14

for the LDAC register mode of operation. This flexibility is

useful in applications when the user wants to simultaneously

update select channels while the rest of the channels are

synchronously updating.

Writing to the DAC using Command 110 loads the 4-bit LDAC

the LDAC pin works normally. Setting the bits to 1 means that

the DAC register is updated, regardless of the state of the LDAC

pin. See Figure 68 for the contents of the input shift register

during the LDAC register setup command.

Table 13. LDAC Register Mode of Operation on the 10-Lead

LFCSP (Load DAC Register)

LDAC Bits

(DB3 to DB0)

LDAC Mode of Operation

Normal operation (default), DAC register

update is controlled by the write command.

The DAC registers are updated after new data

is read in.

Table 14. LDAC Register Mode of Operation on the 14-Lead

TSSOP (Load DAC Register)

LDAC Bits

(DB3 to DB0)

LDAC Pin

LDAC Operation

1/0

Determined by the LDAC pin.

x = don’t

care

The DAC registers are updated

after new data is read in.

Figure 68. LDAC Setup Command

DB15 DB14 DB13 DB12 DB11 DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DAC D DAC C DAC B DAC A

COMMAND

DAC ADDRESS

(DON’T CARE)

DON’T CARE

DAC SELECT

(0 = LDAC PIN ENABLED)

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