AD5665BCPZ-R2 datasheet(24/36 Pages) AD

24 / 36 page

AD5625R/AD5645R/AD5665R, AD5625/AD5665

Data Sheet

Rev. C | Page 24 of 36

EXTERNAL REFERENCE

The VREFIN pin on the AD56x5R allows the use of an external

reference if the application requires it. The default condition of

the on-chip reference is off at power-up. All devices can be

operated from a single 2.7 V to 5.5 V supply.

SERIAL INTERFACE

The AD56x5R/AD56x5 have 2-wire I2C-compatible serial inter-

faces. The AD56x5R/AD56x5 can be connected to an I2C bus as

a slave device, under the control of a master device. See Figure 3

for a timing diagram of a typical write sequence.

The AD56x5R/AD56x5 support standard (100 kHz), fast

(400 kHz), and high speed (3.4 MHz) data transfer modes.

High speed operation is only available on selected models. See

the Ordering Guide for a full list of models. Support is not

provided for 10-bit addressing and general call addressing.

The AD56x5R/AD56x5 each has a 7-bit slave address. The

10-lead and 12-ball versions of the part have a slave address

whose five MSBs are 00011, and the two LSBs are set by the

state of the ADDR address pin, which determines the state of

the A0 and A1 address bits. The 14-lead versions of the part

have a slave address whose three MSBs are 001, and the four

LSBs are set by the ADDR1 and ADDR2 address pins, which

determine the state of the A0 and A1 and A2 and A3 address

bits, respectively.

The facility to make hardwired changes to the ADDR pin allows

the user to incorporate up to three of these devices on one bus,

as outlined in Table 9.

Table 9. ADDR Pin Settings (10-Lead and 12-Ball Packages)

ADDR Pin Connection

VDD

GND

The facility to make hardwired changes to the ADDR1 and the

ADDR2 pins allows the user to incorporate up to nine of these

devices on one bus, as outlined in Table 10.

Table 10. ADDR1, ADDR2 Pin Settings (14-Lead Package)

ADDR2 Pin

Connection

ADDR1 Pin

Connection

VDD

GND

VDD

GND

VDD

GND

The 2-wire serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a start

condition when a high-to-low transition on the SDA line

occurs while SCL is high. The following byte is the address

byte, which consists of the 7-bit slave address. The slave

address corresponding to the transmitted address responds

by pulling SDA low during the ninth clock pulse (this is

termed the acknowledge bit). At this stage, all other devices

on the bus remain idle while the selected device waits for

data to be written to or read from its shift register.

2. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge

bit). The transitions on the SDA line must occur during the

low period of SCL and remain stable during the high

period of SCL.

3. When all data bits have been read or written, a stop

condition is established. In write mode, the master pulls

the SDA line high during the 10th clock pulse to establish a

stop condition. In read mode, the master issues a no

acknowledge for the ninth clock pulse (that is, the SDA line

remains high). The master brings the SDA line low before

the 10th clock pulse, and then high during the 10th clock

pulse to establish a stop condition.

WRITE OPERATION

When writing to the AD56x5R/AD56x5, the user must begin

with a start command followed by an address byte (R/W = 0),

after which the DAC acknowledges that it is prepared to receive

data by pulling SDA low. The AD5665 requires two bytes of

data for the DAC and a command byte that controls various

DAC functions. Three bytes of data must, therefore, be written

to the DAC, the command byte followed by the most significant

data byte and the least significant data byte, as shown in Figure 58

and Figure 59. After these data bytes are acknowledged by the

AD56x5R/AD56x5, a stop condition follows.

READ OPERATION

When reading data back from the AD56x5R/AD56x5, the

user begins with a start command followed by an address byte

(R/W = 1), after which the DAC acknowledges that it is prepared

to transmit data by pulling SDA low. Two bytes of data are then

read from the DAC, which are both acknowledged by the master

as shown in Figure 60 and Figure 61. A stop condition follows.

AD5665BCPZ-R2 数据表(PDF) 24 Page - Analog Devices

AD5665BCPZ-R2 数据表(HTML) 24 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

数据表下载