AD5665BCPZ-R2 datasheet(26/36 Pages) AD

26 / 36 page

AD5625R/AD5645R/AD5665R, AD5625/AD5665

Data Sheet

Rev. C | Page 26 of 36

Figure 61. I2C Read Operation (14-Lead Package)

Figure 62. Placing the AD56x5RBRUZ-2/AD56x5RBRUZ-2REEL7 in High Speed Mode

HIGH SPEED MODE

Some models offer high speed serial communication with a

clock frequency of 3.4 MHz. See the Ordering Guide for a full

list of models.

High speed mode communication commences after the master

addresses all devices connected to the bus with the Master Code

00001XXX to indicate that a high speed mode transfer is to

begin. No device connected to the bus is permitted to acknowl-

edge the high speed master code; therefore, the code is followed

by a no acknowledge. Next, the master must issue a repeated

start followed by the device address. The selected device then

acknowledges its address. All devices continue to operate in

high speed mode until the master issues a stop condition. When

the stop condition is issued, the devices return to standard/fast

mode. The part also returns to standard/fast mode when CLR is

activated while the part is in high speed mode.

INPUT SHIFT REGISTER

The input shift register is 24 bits wide. Data is loaded into the

device as a 24-bit word under the control of a serial clock

input, SCL. The timing diagram for this operation is shown in

Figure 3. The eight MSBs make up the command byte. DB23

is reserved and should always be set to 0 when writing to the

device. DB22 (S) is used to select multiple byte operation.

The next three bits are the command bits (C2, C1, and C0)

that control the mode of operation of the device. See Table 11

for details. The last three bits of the first byte are the address bits

(A2, A1, and A0). See Table 12 for details. The rest of the bits

are the 16-/14-/12-bit data-word. The data-word comprises the

16-/14-/12-bit input code followed by two or four don’t care bits

for the AD5645R and the AD5625R/AD5625, respectively (see

Figure 65 through Figure 67).

MULTIPLE BYTE OPERATION

Multiple byte operation is supported on the AD56x5R/AD56x5.

A 2-byte operation is useful for applications that require fast

DAC updating and do not need to change the command byte.

The S bit (DB22) in the command register can be set to 1 for

2-byte mode of operation (see Figure 64). For standard 3-byte

and 4-byte operation, the S bit (DB22) in the command byte

should be set to 0 (see Figure 63).

FRAME 2

COMMAND BYTE

FRAME 1

SLAVE ADDRESS

SCL

START BY

MASTER

ACK. BY

AD56x5

ACK. BY

MASTER

SDA

R/W

DB23

DB22 DB21 DB20 DB19 DB18 DB17 DB16

ACK. BY

MASTER

NO ACK.

FRAME 4

LEAST SIGNIFICANT

DATA BYTE

FRAME 3

MOST SIGNIFICANT

DATA BYTE

STOP BY

MASTER

SCL

(CONTINUED)

SDA

(CONTINUED)

DB15 DB14 DB13 DB12 DB11 DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

SCL

0000

R/W

SDA

NO ACK.

START BY

MASTER

ACK. BY

AD56x5

HS-MODE

MASTER CODE

SERIAL BUS

ADDRESS BYTE

FAST MODE

HIGH-SPEED MODE

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