AD8331ARQZ-R7 datasheet(32/56 Pages) AD

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AD8331/AD8332/AD8334

Rev. G | Page 32 of 56

with gains less than 40 dB. The exact values of these components

can be selected empirically.

An antialiasing noise filter is typically used with an ADC. Filter

requirements are application dependent.

When the ADC resides on a separate board, the majority of

filter components should be placed nearby to suppress noise

picked up between boards and to mitigate charge kickback from

the ADC inputs. Any series resistance beyond that required for

output stability should be placed on the ADC board. Figure 85

shows a second-order, low-pass filter with a bandwidth of 20 MHz.

The capacitor is chosen in conjunction with the 10 pF input

capacitance of the ADC.

18pF

OPTIONAL

BACKPLANE

0.1µF

ADC

84.5Ω

158Ω

1.5µH

Figure 85. 20 MHz Second-Order, Low-Pass Filter

DRIVING ADCs

The output drive accommodates a wide range of ADCs. The

noise floor requirements of the VGA depend on a number of

application factors, including bit resolution, sampling rate, full-

scale voltage, and the bandwidth of the noise/antialias filter. The

output noise floor and gain range can be adjusted by selecting

HI or LO gain mode.

The relative noise and distortion performance of the two gain

modes can be compared in Figure 25 and Figure 31 through

Figure 41. The 48 nV/√Hz noise floor of the LO gain mode is

suited to converters with higher sampling rates or resolutions

(such as 12 bits). Both gain modes can accommodate ADC full-

scale voltages as high as 4 V p-p. Because distortion performance

remains favorable for output voltages as high as 4 V p-p (see

Figure 36), it is possible to lower the output-referred noise even

further by using a resistive attenuator (or transformer) at the

output. The circuit in Figure 86 has an output full-scale range of

2 V p-p, a gain range of −10.5 dB to +37.5 dB, and an output

noise floor of 24 nV/√Hz, making it suitable for some 14-bit

ADC applications.

ADC

AD6644

187Ω

2:1

187Ω

374Ω

VOH

VOL

LPF

4V p-p DIFF,

48nV/ Hz

2V p-p DIFF,

24nV/ Hz

Figure 86. Adjusting the Noise Floor for 14-Bit ADCs

OVERLOAD

These devices respond gracefully to large signals that overload

its input stage and to normal signals that overload the VGA

when the gain is set unexpectedly high. Each stage is designed

for clean-limited overload waveforms and fast recovery when

gain setting or input amplitude is reduced.

Signals larger than ±275 mV at the LNA input are clipped to

5 V p-p differential prior to the input of the VGA. Figure 48

shows the response to a 1 V p-p input burst. The symmetric

overload waveform is important for applications, such as CW

Doppler ultrasound, where the spectrum of the LNA outputs

during overload is critical. The input stage is also designed to

accommodate signals as high as ±2.5 V without triggering the

slow-settling ESD input protection diodes.

Both stages of the VGA are susceptible to overload. Post-

amplifier limiting is more common and results in the clean-

limited output characteristics found in Figure 49. Recovery is fast in

all cases. The graph in Figure 87 summarizes the combinations of

input signal and gain that lead to the different types of overload.

LO GAIN

MODE

15mV

–4.5

25mV

X-AMP

OVERLOAD

POSTAMP

OVERLOAD

X-AMP

OVERLOAD

POSTAMP

OVERLOAD

29dB

43.5

INPUT AMPLITUDE (V)

0.275

0.1

10m

24.5dB

HI GAIN

MODE

4mV

7.5

25mV

41dB

56.5

INPUT AMPLITUDE (V)

24.5dB

0.275

0.1

10m

Figure 87. Overload Gain and Signal Conditions

The clamp interface mentioned in the Output Clamping section

controls the maximum output swing of the postamp and its

overload response. When the clamp feature is not used, the

output level defaults to approximately 4.5 V p-p differential

centered at 2.5 V common mode. When other common-mode

levels are set through the VCM pin, the value of RCLMP should be

selected for graceful overload. A value of 8.3 kΩ or less is

recommended for 1.5 V or 3.5 V common-mode levels (7.2 kΩ

for HI gain mode). This limits the output swing to just above

2 V p-p differential.

OPTIONAL INPUT OVERLOAD PROTECTION

Applications in which high transients are applied to the LNA

input can benefit from the use of clamp diodes. A pair of back-

to-back Schottky diodes can reduce these transients to manageable

levels. Figure 88 illustrates how such a diode protection scheme

can be connected.

LON

VPSL

INH

COMM

ENBL

0.1µF

RSH

CIZ

RIZ

CSH

OPTIONAL

SCHOTTKY

OVERLOAD

CLAMP

BAS40-04

Figure 88. Input Overload Clamping

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