AD8331ARQZ-R7 datasheet(25/56 Pages) AD

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AD8331/AD8332/AD8334

Rev. G | Page 25 of 56

The linear-in-dB, gain control interface is trimmed for slope and

absolute accuracy. The gain range is +48 dB, extending from

−4.5 dB to +43.5 dB in LO gain and +7.5 dB to +55.5 dB in HI

gain mode. The slope of the gain control interface is 50 dB/V,

and the gain control range is 40 mV to 1 V. Equation 1 and

Equation 2 are the expressions for gain.

GAIN (dB) = 50 (dB/V) × VGAIN − 6.5 dB, (HILO = LO)

(1)

GAIN (dB) = 50 (dB/V) × VGAIN + 5.5 dB, (HILO = HI)

(2)

The ideal gain characteristics are shown in Figure 73.

–10

0.2

0.4

0.6

0.8

1.0

1.1

VGAIN (V)

HILO = HI

HILO = LO

ASCENDING GAIN MODE

DESCENDING GAIN MODE

(WHERE AVAILABLE)

Figure 73. Ideal Gain Control Characteristics

The gain slope is negative with MODE pulled high (where

available), as follows:

GAIN (dB) = −50 (dB/V) × VGAIN + 45.5 dB, (HILO = LO)

(3)

GAIN (dB) = −50 (dB/V) × VGAIN + 57.5 dB, (HILO = HI)

(4)

The LNA converts a single-ended input to a differential output

with a voltage gain of 19 dB. If only one output is used, the gain

is 13 dB. The inverting output is used for active input impedance

termination. Each of the LNA outputs is capacitively coupled to

a VGA input. The VGA consists of an attenuator with a range of

48 dB followed by an amplifier with 21 dB of gain for a net gain

range of −27 dB to +21 dB. The X-AMP, gain interpolation

technique results in low gain error and uniform bandwidth, and

differential signal paths minimize distortion.

The final stage is a logic programmable amplifier with gains of

3.5 dB or 15.5 dB. The LO and HI gain modes are optimized for

12-bit and 10-bit ADC applications, in terms of output-referred

noise and absolute gain range. Output voltage limiting can be

programmed by the user.

LOW NOISE AMPLIFIER (LNA)

Good noise performance in the AD8331/AD8332/AD8334

relies on a proprietary ultralow noise preamplifier at the beginning

of the signal chain, which minimizes the noise contribution in the

following VGA. Active impedance control optimizes noise per-

formance for applications that benefit from input matching.

A simplified schematic of the LNA is shown in Figure 74. INH

is capacitively coupled to the source. A bias generator establishes dc

input bias voltages of 3.25 V and centers the output common-

mode levels at 2.5 V. A capacitor CLMD (can be the same value as

the input coupling capacitor CINH) is connected from the LMD

pin to ground to decouple the LMD bus. The LMD pin is not

useable for configuring the LNA as a differential input amplifier.

CINH

CSH

VPOS

VCM

BIAS

LOP

INH

3.25V

–a

LON

VGA

2.5V

CLMD

LMD

CIZ

RIZ

60Ω

40Ω

80Ω

Figure 74. Simplified LNA Schematic

The LNA supports differential output voltages as high as 5 V p-p,

with positive and negative excursions of ±1.25 V, about a

common-mode voltage of 2.5 V. Because the differential gain

magnitude is 9, the maximum input signal before saturation is

±275 mV or +550 mV p-p. Overload protection ensures quick

recovery time from large input voltages. Because the inputs are

capacitively coupled to a bias voltage near midsupply, very large

inputs can be handled without interacting with the ESD protection.

Low value feedback resistors and the current-driving capability

of the output stage allow the LNA to achieve a low input-referred

voltage noise of 0.74 nV/√Hz. This is achieved with a current

consumption of only 11 mA per channel (55 mW). On-chip

resistor matching results in precise single-ended gains of 4.5×

(9× differential), critical for accurate impedance control. The use

of a fully differential topology and negative feedback minimizes

distortion. Low HD2 is particularly important in second harmonic

ultrasound imaging applications. Differential signaling enables

smaller swings at each output, further reducing third-order

distortion.

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