AD7980BCPZ-R2 datasheet(21/28 Pages) AD

21 / 28 page

Data Sheet

AD7980

Rev. C | Page 21 of 28

CHAIN MODE, WITHOUT BUSY INDICATOR

This mode can be used to daisy-chain multiple AD7980s on a

3-wire serial interface. This feature is useful for reducing

component count and wiring connections, for example, in

isolated multi-converter applications or for systems with a

limited interfacing capacity. Data readback is analogous to

clocking a shift register.

A connection diagram example using two AD7980s is shown in

Figure 39, and the corresponding timing is given in Figure 40.

When SDI and CNV are low, SDO is driven low. With SCK low,

a rising edge on CNV initiates a conversion, selects the chain

mode, and disables the Busy indicator. In this mode, CNV is

held high during the conversion phase and the subsequent data

readback. When the conversion is complete, the MSB is output

onto SDO and the AD7980 enters the acquisition phase and

powers down. The remaining data bits stored in the internal

shift register are clocked by subsequent SCK falling edges. For

each ADC, SDI feeds the input of the internal shift register and

is clocked by the SCK falling edge. Each ADC in the chain

outputs its data MSB first, and 16 × N clocks are required to

readback the N ADCs. The data is valid on both SCK edges.

Although the rising edge can be used to capture the data, a

digital host using the SCK falling edge allows a faster reading

rate and, consequently, more AD7980s in the chain, provided

the digital host has an acceptable hold time. The maximum

conversion rate may be reduced due to the total readback time.

DIGITAL HOST

CONVERT

CLK

DATA IN

AD7980 SDO

SDI

CNV

SCK

AD7980 SDO

SDI

CNV

SCK

Figure 39. Chain Mode Without Busy Indicator Connection Diagram

tCONV

tCYC

tSSDISCK

tSCKL

tSCK

tHSDISC

tACQ

AQUISITION

tSSDICNV

AQUISITION

tSCKH

CONVERSION

SDOA = SDIB

tHSDICNV

SCK

CNV

SDIA = 0

SDOB

tEN

DA15

DA14

DA13

DB15

DB14

DB13

DB1

DB0

DA15

DA14

DA0

DA1

DA0

tHSDO

tDSDO

Figure 40. Chain Mode Without Busy Indicator Serial Interface Timing

AD7980BCPZ-R2 数据表(PDF) 21 Page - Analog Devices

AD7980BCPZ-R2 数据表(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表下载