AD7980BCPZ-R2 datasheet(22/28 Pages) AD

22 / 28 page

AD7980

Data Sheet

Rev. C | Page 22 of 28

CHAIN MODE WITH BUSY INDICATOR

This mode can also be used to daisy-chain multiple AD7980s

on a 3-wire serial interface while providing a busy indicator.

This feature is useful for reducing component count and wiring

connections, for example, in isolated multiconverter applications or

for systems with a limited interfacing capacity. Data readback is

analogous to clocking a shift register.

A connection diagram example using three AD7980s is shown

in Figure 41, and the corresponding timing is given in Figure 42.

When SDI and CNV are low, SDO is driven low. With SCK

high, a rising edge on CNV initiates a conversion, selects the

chain mode, and enables the busy indicator feature. In this

mode, CNV is held high during the conversion phase and the

subsequent data readback. When all ADCs in the chain have

completed their conversions, the SDO pin of the ADC closest to

the digital host (see the AD7980 ADC labeled C in Figure 41) is

driven high. This transition on SDO can be used as a busy

indicator to trigger the data readback controlled by the digital

host. The AD7980 then enters the acquisition phase and powers

down. The data bits stored in the internal shift register are

clocked out, MSB first, by subsequent SCK falling edges. For

each ADC, SDI feeds the input of the internal shift register and

is clocked by the SCK falling edge. Each ADC in the chain

outputs its data MSB first, and 16 × N + 1 clocks are required to

readback the N ADCs. Although the rising edge can be used to

capture the data, a digital host using the SCK falling edge allows a

faster reading rate and, consequently, more AD7980s in the chain,

provided the digital host has an acceptable hold time.

AD7980

SDO

SDI

DATA IN

IRQ

DIGITAL HOST

CONVERT

CLK

CNV

SCK

AD7980

SDO

SDI

CNV

SCK

AD7980

SDO

SDI

CNV

SCK

Figure 41. Chain Mode with Busy Indicator Connection Diagram

tCONV

tCYC

tSSDISCK

tSCKH

tSCK

tHSDISC

tACQ

tDSDOSDI

tDSDODSI

AQUISITION

tSSDICNV

AQUISITION

tSCKL

CONVERSION

tHSDICNV

SCK

CNV = SDIA

SDOA = SDIB

SDOB = SDIC

SDOC

tEN

DA15

DA14

DA13

DB15

DB14

DB13

DC15

DC14

DC13

DB1

DB0

DA15

DA14

DA1

DA0

DC1

DC0

DB15

DB14

DA0

DA1

DB0

DB1

DA14

DA15

DA1

DA0

tHSDO

tDSDO

tDSDOSDI

Figure 42. Chain Mode with Busy Indicator Serial Interface Timing

AD7980BCPZ-R2 数据表(PDF) 22 Page - Analog Devices

AD7980BCPZ-R2 数据表(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表下载

链接网址

AD7980BCPZ-R2 数据表(PDF) 22 Page - Analog Devices

AD7980BCPZ-R2 数据表(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表 下载

链接网址

数据表下载