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MPC8314ECVRAGDA 数据表(PDF) 22 Page - Freescale Semiconductor, Inc |
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MPC8314ECVRAGDA 数据表(HTML) 22 Page - Freescale Semiconductor, Inc |
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22 / 101 page ![]() MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2 22 Freescale Semiconductor DUART This figure provides the AC test load for the DDR bus. Figure 8. DDR AC Test Load 8DUART This section describes the DC and AC electrical specifications for the DUART interface. 8.1 DUART DC Electrical Characteristics This table lists the DC electrical characteristics for the DUART interface. 8.2 DUART AC Electrical Specifications This table lists the AC timing parameters for the DUART interface. 9 Ethernet: Three-Speed Ethernet, MII Management This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII management. Table 21. DUART DC Electrical Characteristics Parameter Symbol Min Max Unit High-level input voltage VIH 2.1 NVDD + 0.3 V Low-level input voltage NVDD VIL –0.3 0.8 V High-level output voltage, IOH = –100 AVOH NVDD – 0.2 — V Low-level output voltage, IOL = 100 AVOL —0.2 V Input current (0 V V IN NVDD) IIN —± 5 A Table 22. DUART AC Timing Specifications Parameter Value Unit Note Minimum baud rate 256 baud — Maximum baud rate > 1,000,000 baud 1 Oversample rate 16 — 2 Note: 1. Actual attainable baud rate is limited by the latency of interrupt processing. 2. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each sixteenth sample. Output Z0 = 50 GVDD/2 RL = 50 |
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