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MPC8314ECVRAGDA 数据表(PDF) 85 Page - Freescale Semiconductor, Inc |
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MPC8314ECVRAGDA 数据表(HTML) 85 Page - Freescale Semiconductor, Inc |
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85 / 101 page  MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 85 Clocking 23 Clocking This figure shows the internal distribution of clocks within the MPC8314E 1 Multiplication factor M = 1, 1.5, 2, 2.5, and 3. Value is decided by RCWLR[COREPLL]. 2 Multiplication factor L = 2, 3, 4 and 5. Value is decided by RCWLR[SPMF]. Figure 60. MPC8314E Clock Subsystem System LBC LCLK[0:1] e300c3 core csb_clk to rest csb_clk Local Bus PCI_CLK_OUT[0:2] PCI_SYNC_OUT PCI_CLK/ Clock Unit of the device lbc_clk _DIV PCI Clock PCI_SYNC_IN Memory Device /n To local bus Clock Divider ( 2) 3 MEMC_MCK MEMC_MCK DDR ddr_clk DDR Memory Device PLL to DDR memory controller Clock CFG_CLKIN /2 Divider Divider 1 0 USB Mac USB PHY PLL eTSEC Protocol Converter GTX_CLK125 125-MHz source SYS_XTAL_IN SYS_XTAL_OUT mux Crystal SYS_CLK_IN USB_XTAL_IN USB_XTAL_OUT Crystal USB_CLK_IN /1,/2 RTC_CLK (32 kHz) RTC Sys Ref Core PLL core_clk x L2 x M1 TDM /n PCI Express Protocol Converter 125/100 MHz PLL PCVTR Mux SerDes PHY + - SD_REF_CLK_B SD_REF_CLK MPC8314E |
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