MCR03EZPFX4021 datasheet(15/35 Pages) IRF

15 / 35 page

Rev 4.0

PD-97516

IR3853MPbF

Thermal Shutdown

Temperature sensing is provided inside IR3853.

The trip threshold is typically set to 140oC. When

trip threshold is exceeded, thermal shutdown

turns off both MOSFETs and discharges the soft

start capacitor.

Automatic restart is initiated when the sensed

temperature drops within the operating range.

There is a 20oC hysteresis in the thermal

shutdown threshold.

Fig. 8b. Application Circuit for Simultaneous

Sequencing

Simultaneous Powerup

Vo1

Vo2

Output Voltage Sequencing

The

IR3853

can

accommodate

user

programmable sequencing options using Seq,

Enable and Power Good pins.

Boot

Vcc

Comp

Gnd

PGnd

OCSet

SS/ SD

4.5V <Vcc<5.5V

Vo(master)

PGood

Enable

1.5V <Vin<16V

Vin

Seq

Boot

Vcc

Comp

Gnd

PGnd

OCSet

SS/ SD

4.5V <Vcc<5.5V

Vo(slave)

PGood

Enable

1.5V <Vin<16V

Vin

Seq

Vo(master)

Fig. 8a. Simultaneous Power-up of the slave

with respect to the master.

Through these pins, voltage sequencing such as

simultaneous

and

sequential

can

implemented. Figure 8. shows simultaneous

sequencing

configurations.

simultaneous

power-up, the voltage at the Seq pin of the slave

reaches 0.7V before the Fb pin of the master. For

E/RF =RC/RD, therefore, the output voltage of

the slave follows that of the master until the

voltage at the Seq pin of the slave reaches 0.7 V.

After the voltage at the Seq pin of the slave

exceeds 0.85V, the internal 0.7V reference of

the slave dictates its output voltage.

Power-Good and Over-voltage Protection

If the output voltage exceeds the over voltage

threshold, an over voltage trip signal asserts, this

will result to turn off the high side driver and turn

on the low side driver until the Vsns voltage

drops below 1.15*Vref threshold. Both drivers are

latched off until a reset performed by cycling

either Vcc or Enable.

The

OVP

threshold

can

externally

programmed to user defined value. Figure 10

shows the response in over-voltage condition.

The V

sns pin

forms an input to a window

comparator whose upper and lower thresholds

are 0.805V and 0.595V, respectively. Hence, the

Power Good signal is flagged when the V

sns pin

voltage is within the PGood window, i.e.

between 0.595V to 0.805V, as shown in figure 9.

The PGood pin is open drain and it needs to be

externally pulled high. High state indicates that

output is in regulation. Figure 9a shows the

PGood

timing

diagram

for

non-tracking

operation. In this case, during startup, PGood

goes high after the SS voltage reaches 2.1V if

the

Vsns

voltage

within

the

PGood

comparator window. Figure 9.a and Figure 9.b

also show a 256 cycle delay between the Vsns

voltage entering within the thresholds defined by

the PGood window and PGood going high.

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