ADRF6702ACPZ-R7 datasheet(9/36 Pages) AD

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Data Sheet

ADRF6702

Rev. B | Page 9 of 36

Pin No.

Mnemonic

Description

CLK

Serial Clock Input. This serial clock input is used to clock in the serial data to the

registers. The data is latched into the 24-bit shift register on the CLK rising edge.

Maximum clock frequency is 20 MHz.

Latch Enable. When the LE input pin goes high, the data stored in the shift registers is

loaded into one of the six registers, the relevant latch being selected by the first three

control bits of the 24-bit word.

ENOP

Modulator Output Enable/Disable. See Table 6.

18, 19, 32, 33

QP, QN, IN, IP

Modulator Baseband Inputs. Differential in-phase and quadrature baseband inputs.

These inputs should be dc-biased to 0.5 V.

RFOUT

RF Output. Single-ended, 50 Ω internally biased RF output. RFOUT must be ac-coupled

to its load.

LOSEL

LO Select. This digital input pin determines whether the LOP and LON pins operate as

inputs or outputs. This pin should not be left floating. LOP and LON become inputs if

the LOSEL pin is set low and the LDRV bit of Register 5 is set low. External LO drive

must be a 2× LO. In addition to setting LOSEL and LDRV low and providing an external

2× LO, the LXL bit of Register 5 (DB4) must be set to 1 to direct the external LO to the

IQ modulator. LON and LOP become outputs when LOSEL is high or if the LDRV bit of

LDIV bit of Register 5 (DB5) to 1 or 0 respectively (see Table 7).

37, 38

LON, LOP

Local Oscillator Input/Output. The internally generated 1× LO or 2× LO is available on

these pins. When internal LO generation is disabled, an external 1× LO or 2× LO can be

applied to these pins.

VTUNE

VCO Control Voltage Input. This pin is driven by the output of the loop filter. Nominal

input voltage range on this pin is 1.3 V to 2.5 V. If the external VCO mode is activated,

this pin can be left open.

DECL3

Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 μF capacitor

between this pin and ground.

Exposed Paddle. The exposed paddle should be soldered to a low impedance

ground plane.

Table 6. Enabling RFOUT

ENOP

RFOUT

Disabled

Enabled

1 X = don’t care.

Table 7. LO Port Configuration1, 2

LON/LOP Function

LOSEL

Input (2× LO)

Output (Disabled)

Output (1× LO)

Output (2× LO)

1 X = don’t care.

2 LOSEL should not be left floating.

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