ADRF6702ACPZ-R7 datasheet(24/36 Pages) AD

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ADRF6702

Data Sheet

Rev. B | Page 24 of 36

REFERENCE PATH CONTROL (DEFAULT:

0x0AA7E4)

With Register 4, Bits[2:0] set to 100, the on-chip charge pump,

PFD, and reference path control register is programmed as

shown in Figure 45.

CP Current

The nominal charge pump current can be set to 250 μA, 500 μA,

750 μA, or 1000 μA using DB10 and DB11 of Register 4 and by

setting DB18 to 0 (CP reference source).

In this mode, no external RSET is required. If DB18 is set to 1,

the four nominal charge pump currents (INOMINAL) can be

externally tweaked according to the following equation:

−

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

217

NOMINAL

SET

(3)

where ICP is the base charge pump current in microamps.

The PFD phase offset multiplier (θPFD,OFS), which is set by

Bits[16:12] of Register 4, causes the PLL to lock with a

nominally fixed phase offset between the PFD reference signal

and the divided-down VCO signal. This phase offset is used

to linearize the PFD-to-CP transfer function and can improve

fractional spurs. The magnitude of the phase offset is deter-

mined by the following equation:

MULT

OFS

PFD

(deg)

ΔΦ

(4)

The default value of the phase offset multiplier (10 × 22.5°)

should be set to a recommended value of 6 × 22.5°.

This phase offset can be either positive or negative depending

on the value of DB17 in Register 4.

The reference frequency applied to the PFD can be manipulated

using the internal reference path source. The external reference

frequency applied can be internally scaled in frequency by 2×,

1×, 0.5×, or 0.25×. This allows a broader range of reference

frequency selections while keeping the reference frequency

applied to the PFD within an acceptable range.

The device also has a MUXOUT pin that can be programmed

to output a selection of several internal signals. The default

mode is to provide a lock-detect output to allow the user to

verify when the PLL has locked to the target frequency. In

addition, several other internal signals can be passed to the

MUXOUT pin as described in Figure 35.

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