2-Port SS/HS USB Hub Controller

Datasheet

SMSC USB5532B

25

Revision 1.2 (05-31-13)

DATASHEET

Note: For the following SMBus tables:

Figure 5.12 Block Write

5.2.2.2

Block Read

specification’s requirement for a change in the transfer direction.

Figure 5.13 Block Read

5.2.2.3

Invalid Protocol Response Behavior

Note that any attempt to update registers with an invalid protocol will not be updated. The only valid

protocols are write block and read block (described above), where the hub only responds to the 7-bit

hardware selected slave addresses (0101100b or 0101101b). Additionally, the only valid registers for

the hub are outlined in the USB5532B Configuration Release Notes documentation.

5.2.3

Slave Device Timeout

Devices in a transfer can abort the transfer in progress and release the bus when any single clock low

condition within or after the transfer of the interrupted data byte. Slave devices must reset their

Note: Some simple devices do not contain a clock low drive circuit; this simple kind of device typically

resets its communications port after a start or stop condition. The slave device timeout must

be implemented.

5.2.4

Stretching the SCLK Signal

The hub supports stretching of the SCLK by other devices on the SMBus. The hub will stretch the

clock as needed.

Denotes Master-to-Slave

Denotes Slave-to-Master

S

Slave Address

SMBus RAM Buffer Offset

Wr

A

1

7

1

1

8/16

A

1

...

1

81

Byte Count = N

A

Data byte 1

A

Data byte 2

A

81

1

1

88

Data byte N

A

P

1

S

S

Slave Address

SMBus RAM

Buffer Offset

Wr

1

7

1

1

8/16

A

1

Slave Address

Rd

A

71

1

...

A

81

1

1

88

1

81

P

A

A

A

A

Byte Count = N

Data byte 2

Data byte 1

Data byte N