2-Port SS/HS USB Hub Controller

Datasheet

SMSC USB5532B

27

Revision 1.2 (05-31-13)

DATASHEET

5.3

Reset

There are two different resets that the device experiences. One is a hardware reset (either from the

internal POR reset circuit or via the RESET_N pin) and the second is a USB Bus Reset.

5.3.1

Internal POR

All reset timing parameters are guaranteed by design.

5.3.2

External Hardware Reset

A valid hardware reset is defined as assertion of RESET_N for a minimum of 1

μs after all power

supplies are within operating range.

Assertion of RESET_N (external pin) causes the following:

1. The PHY is disabled, and the differential pairs will be in a high-impedance state.

2. All transactions immediately terminate; no states are saved.

3. All internal registers return to the default state.

4. The external crystal oscillator is halted.

5. The PLL is halted.