2-Port SS/HS USB Hub Controller

Datasheet

Revision 1.2 (05-31-13)

18

SMSC USB5532B

DATASHEET

Figure 5.2 SPI Hi-Speed Read Sequence

5.1.2

Operation of the Dual Hi-Speed Read Sequence

The SPI controller also supports dual data mode (at 30 MHz SPI speed only). When configured in dual

mode, the SPI controller will automatically handle reads going out to the SPI ROM. When the controller

detects a read, the controller drops the SPI_CE_N, and puts out a 0x3B, followed by the 24-bit address.

The SPI controller then puts out a DUMMY byte. The next four clocks clock in the first byte. The data

appears two bits at a time on data out and data in. When the first byte is clocked in a ready signal is

sent back to the processor, and the processor gets one byte.

After the processor gets the first byte, the address will change. If the address is one more than the

last address, the SPI controller will clock out one more byte. If the address in anything other than one

more than the last address, the SPI controller will terminate the transaction by taking SPI_CE_N high.

As long as the addresses are sequential, the SPI Controller will keep clocking in data.

Figure 5.3 SPI Dual Hi-Speed Read Operation

SPI_CEN

SPI_CLK

SPI_DO

SPI_DI

8

0B

MSB

HIGH IMPEDANCE

15 16

12 3 4

05

7

6

ADD.

23 24

ADD.

ADD.

X

39 40

31 32

47 48

55 56

63 64

71 72

80

NN+1

N+2

N+3

N+4

MSB

MSB

SPI

CONTROLLER

SPI

ROM

2-Serial to

8-Parallel

CE#

CLK

SI

SO

ADDRESS

CONTROL

CACHE

SPI_DI

SMSC USB Hub