2-Port SS/HS USB Hub Controller

Datasheet

SMSC USB5532B

17

Revision 1.2 (05-31-13)

DATASHEET

Chapter 5 Interfacing to the USB5532B

The hub will interface to external memory depending on configuration of the USB5532B pins

associated with each interface type. The USB5532B will first check to see whether an external SPI

Flash is present. If not, the USB5532B will operate from internal ROM. If SPI Flash is present, the chip

will operate from the external ROM. Next, the USB5532B will look to receive configuration and

commands from an optional SMBus master (if present). When SMBus is enabled, the SMBus can

operate in either legacy (USB 2.0 only) or advanced mode (access to both USB 2.0 and 3.0 registers).

Next, the USB5532B will look for (optional) configuration present in the internal OTP memory. Any

register settings that are modified via the SMBus interface will overwrite the internal OTP settings.

5.1

SPI Interface

The USB5532B is capable of code execution from an external SPI ROM. On power up, the firmware

looks for an external SPI flash device that contains a valid signature of 2DFU (device firmware upgrade)

beginning at address 0xFFFA. If a valid signature is found, then the external ROM is enabled and the

code execution begins at address 0x0000 in the external SPI device. If a valid signature is not found,

then execution continues from internal ROM. The following sections describe the interface options to

the external SPI ROM.

5.1.1

Operation of the Hi-Speed Read Sequence

The SPI controller will automatically handle code reads going out to the SPI ROM Address. When the

controller detects a read, the controller drops the SPI_CE, and puts out a 0x0B, followed by the 24-bit

address. The SPI controller then puts out a DUMMY byte. The next eight clocks clock in the first byte.

When the first byte is clocked in a ready signal is sent back to the processor, and the processor gets

one byte.

After the processor gets the first byte, its address will change. If the address is one more than the last

address, the SPI controller will clock out one more byte. If the address in anything other than one more

than the last address, the SPI controller will terminate the transaction by taking SPI_CE high. As long

as the addresses are sequential, the SPI Controller will keep clocking in data.

Figure 5.1 SPI Hi-Speed Read Operation

SPI

CONTROLLER

SPI

ROM

Serial to

Parllel

CE#

CLK

SI

SO

SMSC USB Hub

ADDRESS

CONTROL

CACHE

SPI_DI